From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52713) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WOXI1-0002fe-Lo for qemu-devel@nongnu.org; Fri, 14 Mar 2014 14:57:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WOXHx-0000cP-1e for qemu-devel@nongnu.org; Fri, 14 Mar 2014 14:57:05 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:46761) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WOXHw-0000a0-Re for qemu-devel@nongnu.org; Fri, 14 Mar 2014 14:57:00 -0400 From: Peter Maydell Date: Fri, 14 Mar 2014 18:38:01 +0000 Message-Id: <1394822294-14837-13-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1394822294-14837-1-git-send-email-peter.maydell@linaro.org> References: <1394822294-14837-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH v2 12/25] target-arm: A64: List unsupported shift-imm opcodes List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Crosthwaite , patches@linaro.org, Michael Matz , Alexander Graf , Will Newton , Dirk Mueller , Laurent Desnogues , =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall , Richard Henderson Add the remaining unsupported opcodes to the decode switches for the shift-imm and scalar shift-imm categories so we can see what is still to be implemented. Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index e6addf4..2b1ca64 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -6135,9 +6135,15 @@ static void disas_simd_scalar_shift_imm(DisasContext *s, uint32_t insn) handle_vec_simd_sqshrn(s, true, false, is_u, is_u, immh, immb, opcode, rn, rd); break; - default: + case 0x8: /* SRI */ + case 0xc: /* SQSHLU */ + case 0xe: /* SQSHL, UQSHL */ + case 0x1f: /* FCVTZS, FCVTZU */ unsupported_encoding(s, insn); break; + default: + unallocated_encoding(s); + break; } } @@ -7281,11 +7287,14 @@ static void disas_simd_shift_imm(DisasContext *s, uint32_t insn) handle_simd_shift_intfp_conv(s, false, is_q, is_u, immh, immb, opcode, rn, rd); break; + case 0x8: /* SRI */ + case 0xc: /* SQSHLU */ + case 0xe: /* SQSHL, UQSHL */ case 0x1f: /* FCVTZS/ FCVTZU */ unsupported_encoding(s, insn); return; default: - unsupported_encoding(s, insn); + unallocated_encoding(s); return; } } -- 1.9.0