From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Peter Crosthwaite" <peter.crosthwaite@xilinx.com>,
patches@linaro.org, "Michael Matz" <matz@suse.de>,
"Alexander Graf" <agraf@suse.de>,
"Will Newton" <will.newton@linaro.org>,
"Dirk Mueller" <dmueller@suse.de>,
"Laurent Desnogues" <laurent.desnogues@gmail.com>,
"Alex Bennée" <alex.bennee@linaro.org>,
kvmarm@lists.cs.columbia.edu,
"Christoffer Dall" <christoffer.dall@linaro.org>,
"Richard Henderson" <rth@twiddle.net>
Subject: [Qemu-devel] [PATCH v2 08/25] target-arm: A64: Implement SHLL, SHLL2
Date: Fri, 14 Mar 2014 18:37:57 +0000 [thread overview]
Message-ID: <1394822294-14837-9-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1394822294-14837-1-git-send-email-peter.maydell@linaro.org>
Implement the SHLL and SHLL2 instructions from the 2-reg-misc
category.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/translate-a64.c | 32 +++++++++++++++++++++++++++++++-
1 file changed, 31 insertions(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 4562fac..7fca9ff 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -8529,6 +8529,36 @@ static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u,
}
}
+static void handle_shll(DisasContext *s, bool is_q, int size, int rn, int rd)
+{
+ /* Implement SHLL and SHLL2 */
+ int pass;
+ int part = is_q ? 2 : 0;
+ TCGv_i64 tcg_res[2];
+
+ for (pass = 0; pass < 2; pass++) {
+ static NeonGenWidenFn * const widenfns[3] = {
+ gen_helper_neon_widen_u8,
+ gen_helper_neon_widen_u16,
+ tcg_gen_extu_i32_i64,
+ };
+ NeonGenWidenFn *widenfn = widenfns[size];
+ TCGv_i32 tcg_op = tcg_temp_new_i32();
+
+ read_vec_element_i32(s, tcg_op, rn, part + pass, MO_32);
+ tcg_res[pass] = tcg_temp_new_i64();
+ widenfn(tcg_res[pass], tcg_op);
+ tcg_gen_shli_i64(tcg_res[pass], tcg_res[pass], 8 << size);
+
+ tcg_temp_free_i32(tcg_op);
+ }
+
+ for (pass = 0; pass < 2; pass++) {
+ write_vec_element(s, tcg_res[pass], rd, pass, MO_64);
+ tcg_temp_free_i64(tcg_res[pass]);
+ }
+}
+
/* C3.6.17 AdvSIMD two reg misc
* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
* +---+---+---+-----------+------+-----------+--------+-----+------+------+
@@ -8590,7 +8620,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
unallocated_encoding(s);
return;
}
- unsupported_encoding(s, insn);
+ handle_shll(s, is_q, size, rn, rd);
return;
case 0xa: /* CMLT */
if (u == 1) {
--
1.9.0
next prev parent reply other threads:[~2014-03-14 18:57 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-03-14 18:37 [Qemu-devel] [PATCH v2 00/25] A64: Neon patches, sixth set Peter Maydell
2014-03-14 18:37 ` [Qemu-devel] [PATCH v2 01/25] target-arm: A64: Implement PMULL instruction Peter Maydell
2014-03-14 18:37 ` [Qemu-devel] [PATCH v2 02/25] target-arm: A64: Fix bug in add_sub_ext handling of rn Peter Maydell
2014-03-14 18:37 ` [Qemu-devel] [PATCH v2 03/25] target-arm: A64: Add last AdvSIMD Integer to FP ops Peter Maydell
2014-03-14 18:37 ` [Qemu-devel] [PATCH v2 04/25] target-arm: A64: Add FSQRT to C3.6.17 (two misc) Peter Maydell
2014-03-14 18:37 ` [Qemu-devel] [PATCH v2 05/25] target-arm: A64: Add remaining CLS/Z vector ops Peter Maydell
2014-03-14 18:37 ` [Qemu-devel] [PATCH v2 06/25] target-arm: A64: Saturating and narrowing shift ops Peter Maydell
2014-03-14 18:37 ` [Qemu-devel] [PATCH v2 07/25] target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALP Peter Maydell
2014-03-14 18:37 ` Peter Maydell [this message]
2014-03-14 18:37 ` [Qemu-devel] [PATCH v2 09/25] target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructions Peter Maydell
2014-03-14 18:37 ` [Qemu-devel] [PATCH v2 10/25] target-arm: A64: Implement FCVTN Peter Maydell
2014-03-14 18:38 ` [Qemu-devel] [PATCH v2 11/25] target-arm: A64: Implement FCVTL Peter Maydell
2014-03-14 18:38 ` [Qemu-devel] [PATCH v2 12/25] target-arm: A64: List unsupported shift-imm opcodes Peter Maydell
2014-03-14 18:38 ` [Qemu-devel] [PATCH v2 13/25] target-arm: A64: Add FRECPX (reciprocal exponent) Peter Maydell
2014-03-14 18:38 ` [Qemu-devel] [PATCH v2 14/25] target-arm: A64: Implement SRI Peter Maydell
2014-03-14 18:38 ` [Qemu-devel] [PATCH v2 15/25] target-arm: A64: Implement FRINT* Peter Maydell
2014-03-14 18:38 ` [Qemu-devel] [PATCH v2 16/25] exec-all.h: Increase MAX_OP_PER_INSTR for ARM A64 decoder Peter Maydell
2014-03-14 18:38 ` [Qemu-devel] [PATCH v2 17/25] target-arm: A64: Handle saturating left shifts SQSHL, SQSHLU, UQSHL Peter Maydell
2014-03-14 18:38 ` [Qemu-devel] [PATCH v2 18/25] target-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categories Peter Maydell
2014-03-14 18:38 ` [Qemu-devel] [PATCH v2 19/25] softfloat: export squash_input_denormal functions Peter Maydell
2014-03-14 18:38 ` [Qemu-devel] [PATCH v2 20/25] target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPE Peter Maydell
2014-03-14 18:38 ` [Qemu-devel] [PATCH v2 21/25] target-arm: A64: Move handle_2misc_narrow function Peter Maydell
2014-03-14 18:38 ` [Qemu-devel] [PATCH v2 22/25] target-arm: A64: Implement scalar saturating narrow ops Peter Maydell
2014-03-14 18:38 ` [Qemu-devel] [PATCH v2 23/25] target-arm: A64: Implement FCVTXN Peter Maydell
2014-03-14 18:38 ` [Qemu-devel] [PATCH v2 24/25] target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate) Peter Maydell
2014-03-14 18:38 ` [Qemu-devel] [PATCH v2 25/25] scripts/qemu-binfmt-conf.sh: Add AArch64 registration Peter Maydell
2014-03-14 23:21 ` [Qemu-devel] [PATCH v2 00/25] A64: Neon patches, sixth set Richard Henderson
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