From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52591) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WOXHw-0002VQ-Nn for qemu-devel@nongnu.org; Fri, 14 Mar 2014 14:57:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WOXHv-0000b6-2S for qemu-devel@nongnu.org; Fri, 14 Mar 2014 14:57:00 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:46761) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WOXHu-0000a0-Sd for qemu-devel@nongnu.org; Fri, 14 Mar 2014 14:56:59 -0400 From: Peter Maydell Date: Fri, 14 Mar 2014 18:37:57 +0000 Message-Id: <1394822294-14837-9-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1394822294-14837-1-git-send-email-peter.maydell@linaro.org> References: <1394822294-14837-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH v2 08/25] target-arm: A64: Implement SHLL, SHLL2 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Crosthwaite , patches@linaro.org, Michael Matz , Alexander Graf , Will Newton , Dirk Mueller , Laurent Desnogues , =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall , Richard Henderson Implement the SHLL and SHLL2 instructions from the 2-reg-misc category. Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 32 +++++++++++++++++++++++++++++++- 1 file changed, 31 insertions(+), 1 deletion(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 4562fac..7fca9ff 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -8529,6 +8529,36 @@ static void handle_2misc_pairwise(DisasContext *s, int opcode, bool u, } } +static void handle_shll(DisasContext *s, bool is_q, int size, int rn, int rd) +{ + /* Implement SHLL and SHLL2 */ + int pass; + int part = is_q ? 2 : 0; + TCGv_i64 tcg_res[2]; + + for (pass = 0; pass < 2; pass++) { + static NeonGenWidenFn * const widenfns[3] = { + gen_helper_neon_widen_u8, + gen_helper_neon_widen_u16, + tcg_gen_extu_i32_i64, + }; + NeonGenWidenFn *widenfn = widenfns[size]; + TCGv_i32 tcg_op = tcg_temp_new_i32(); + + read_vec_element_i32(s, tcg_op, rn, part + pass, MO_32); + tcg_res[pass] = tcg_temp_new_i64(); + widenfn(tcg_res[pass], tcg_op); + tcg_gen_shli_i64(tcg_res[pass], tcg_res[pass], 8 << size); + + tcg_temp_free_i32(tcg_op); + } + + for (pass = 0; pass < 2; pass++) { + write_vec_element(s, tcg_res[pass], rd, pass, MO_64); + tcg_temp_free_i64(tcg_res[pass]); + } +} + /* C3.6.17 AdvSIMD two reg misc * 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0 * +---+---+---+-----------+------+-----------+--------+-----+------+------+ @@ -8590,7 +8620,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) unallocated_encoding(s); return; } - unsupported_encoding(s, insn); + handle_shll(s, is_q, size, rn, rd); return; case 0xa: /* CMLT */ if (u == 1) { -- 1.9.0