From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39051) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WOYR3-0000R2-4m for qemu-devel@nongnu.org; Fri, 14 Mar 2014 16:10:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WOYQy-0008UD-Cg for qemu-devel@nongnu.org; Fri, 14 Mar 2014 16:10:29 -0400 Received: from mail-qc0-x236.google.com ([2607:f8b0:400d:c01::236]:60757) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WOYQy-0008U9-8w for qemu-devel@nongnu.org; Fri, 14 Mar 2014 16:10:24 -0400 Received: by mail-qc0-f182.google.com with SMTP id e16so3438553qcx.41 for ; Fri, 14 Mar 2014 13:10:24 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Fri, 14 Mar 2014 13:09:49 -0700 Message-Id: <1394827791-6518-13-git-send-email-rth@twiddle.net> In-Reply-To: <1394827791-6518-1-git-send-email-rth@twiddle.net> References: <1394827791-6518-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PULL 12/14] tcg-aarch64: Support muluh, mulsh List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, aliguori@amazon.com Signed-off-by: Richard Henderson Reviewed-by: Claudio Fontana Tested-by: Claudio Fontana --- tcg/aarch64/tcg-target.c | 12 ++++++++++++ tcg/aarch64/tcg-target.h | 4 ++-- 2 files changed, 14 insertions(+), 2 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index b9dc6bb..9c50820 100644 --- a/tcg/aarch64/tcg-target.c +++ b/tcg/aarch64/tcg-target.c @@ -311,6 +311,8 @@ typedef enum { I3508_LSRV = 0x1ac02400, I3508_ASRV = 0x1ac02800, I3508_RORV = 0x1ac02c00, + I3508_SMULH = 0x9b407c00, + I3508_UMULH = 0x9bc07c00, /* Logical shifted register instructions (without a shift). */ I3510_AND = 0x0a000000, @@ -1565,6 +1567,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, args[5], const_args[4], const_args[5], true); break; + case INDEX_op_muluh_i64: + tcg_out_insn(s, 3508, UMULH, TCG_TYPE_I64, a0, a1, a2); + break; + case INDEX_op_mulsh_i64: + tcg_out_insn(s, 3508, SMULH, TCG_TYPE_I64, a0, a1, a2); + break; + case INDEX_op_mov_i64: case INDEX_op_mov_i32: case INDEX_op_movi_i64: @@ -1694,6 +1703,9 @@ static const TCGTargetOpDef aarch64_op_defs[] = { { INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rwA", "rwMZ" } }, { INDEX_op_sub2_i64, { "r", "r", "rZ", "rZ", "rA", "rMZ" } }, + { INDEX_op_muluh_i64, { "r", "r", "r" } }, + { INDEX_op_mulsh_i64, { "r", "r", "r" } }, + { -1 }, }; diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index f174ebd..c819095 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -89,8 +89,8 @@ typedef enum { #define TCG_TARGET_HAS_sub2_i64 1 #define TCG_TARGET_HAS_mulu2_i64 0 #define TCG_TARGET_HAS_muls2_i64 0 -#define TCG_TARGET_HAS_muluh_i64 0 -#define TCG_TARGET_HAS_mulsh_i64 0 +#define TCG_TARGET_HAS_muluh_i64 1 +#define TCG_TARGET_HAS_mulsh_i64 1 enum { TCG_AREG0 = TCG_REG_X19, -- 1.8.5.3