From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, aliguori@amazon.com
Subject: [Qemu-devel] [PULL 04/14] tcg-aarch64: Implement mov with tcg_out_insn
Date: Fri, 14 Mar 2014 13:09:41 -0700 [thread overview]
Message-ID: <1394827791-6518-5-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1394827791-6518-1-git-send-email-rth@twiddle.net>
Avoid the magic numbers in the current implementation.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
Tested-by: Claudio Fontana <claudio.fontana@huawei.com>
---
tcg/aarch64/tcg-target.c | 24 +++++++++---------------
1 file changed, 9 insertions(+), 15 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index b5f19ad..9b6374d 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -376,13 +376,16 @@ static inline void tcg_out_ldst_12(TCGContext *s,
| op_type << 20 | scaled_uimm << 10 | rn << 5 | rd);
}
-static inline void tcg_out_movr(TCGContext *s, TCGType ext,
- TCGReg rd, TCGReg src)
+/* Register to register move using ORR (shifted register with no shift). */
+static void tcg_out_movr(TCGContext *s, TCGType ext, TCGReg rd, TCGReg rm)
{
- /* register to register move using MOV (shifted register with no shift) */
- /* using MOV 0x2a0003e0 | (shift).. */
- unsigned int base = ext ? 0xaa0003e0 : 0x2a0003e0;
- tcg_out32(s, base | src << 16 | rd);
+ tcg_out_insn(s, 3510, ORR, ext, rd, TCG_REG_XZR, rm);
+}
+
+/* Register to register move using ADDI (move to/from SP). */
+static void tcg_out_movr_sp(TCGContext *s, TCGType ext, TCGReg rd, TCGReg rn)
+{
+ tcg_out_insn(s, 3401, ADDI, ext, rd, rn, 0);
}
static inline void tcg_out_movi_aux(TCGContext *s,
@@ -457,15 +460,6 @@ static inline void tcg_out_ldst(TCGContext *s, enum aarch64_ldst_op_data data,
tcg_out_ldst_r(s, data, type, rd, rn, TCG_REG_TMP);
}
-/* mov alias implemented with add immediate, useful to move to/from SP */
-static inline void tcg_out_movr_sp(TCGContext *s, TCGType ext,
- TCGReg rd, TCGReg rn)
-{
- /* using ADD 0x11000000 | (ext) | rn << 5 | rd */
- unsigned int base = ext ? 0x91000000 : 0x11000000;
- tcg_out32(s, base | rn << 5 | rd);
-}
-
static inline void tcg_out_mov(TCGContext *s,
TCGType type, TCGReg ret, TCGReg arg)
{
--
1.8.5.3
next prev parent reply other threads:[~2014-03-14 20:10 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-03-14 20:09 [Qemu-devel] [PULL 00/14] tcg/aarch64 improvements, part 2 Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 01/14] tcg-aarch64: Introduce tcg_out_insn Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 02/14] tcg-aarch64: Convert shift insns to tcg_out_insn Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 03/14] tcg-aarch64: Introduce tcg_out_insn_3401 Richard Henderson
2014-03-14 20:09 ` Richard Henderson [this message]
2014-03-14 20:09 ` [Qemu-devel] [PULL 05/14] tcg-aarch64: Handle constant operands to add, sub, and compare Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 06/14] tcg-aarch64: Handle constant operands to and, or, xor Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 07/14] tcg-aarch64: Support andc, orc, eqv, not, neg Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 08/14] tcg-aarch64: Support movcond Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 09/14] tcg-aarch64: Use tcg_out_insn for setcond Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 10/14] tcg-aarch64: Support deposit Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 11/14] tcg-aarch64: Support add2, sub2 Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 12/14] tcg-aarch64: Support muluh, mulsh Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 13/14] tcg-aarch64: Support div, rem Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 14/14] tcg-aarch64: Introduce tcg_out_insn_3405 Richard Henderson
2014-03-15 18:24 ` [Qemu-devel] [PULL 00/14] tcg/aarch64 improvements, part 2 Peter Maydell
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