* [Qemu-devel] [PULL 00/14] tcg/aarch64 improvements, part 2
@ 2014-03-14 20:09 Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 01/14] tcg-aarch64: Introduce tcg_out_insn Richard Henderson
` (14 more replies)
0 siblings, 15 replies; 16+ messages in thread
From: Richard Henderson @ 2014-03-14 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, aliguori
Recently reviewed.
It'd be nice if this makes -rc1, since it significantly improves code
generation for the host. But it's no big deal if it's too late.
r~
The following changes since commit b19fc63cadb2815d5bcb1ec25b22849e455cbb31:
Merge remote-tracking branch 'remotes/afaerber/tags/qom-devices-for-2.0' into staging (2014-03-13 21:50:40 +0000)
are available in the git repository at:
git://github.com/rth7680/qemu.git tcg-aarch-6-2
for you to fetch changes up to 582ab779c5cf9c941909faa65e092b6b492e2da6:
tcg-aarch64: Introduce tcg_out_insn_3405 (2014-03-14 11:00:15 -0700)
----------------------------------------------------------------
Richard Henderson (14):
tcg-aarch64: Introduce tcg_out_insn
tcg-aarch64: Convert shift insns to tcg_out_insn
tcg-aarch64: Introduce tcg_out_insn_3401
tcg-aarch64: Implement mov with tcg_out_insn
tcg-aarch64: Handle constant operands to add, sub, and compare
tcg-aarch64: Handle constant operands to and, or, xor
tcg-aarch64: Support andc, orc, eqv, not, neg
tcg-aarch64: Support movcond
tcg-aarch64: Use tcg_out_insn for setcond
tcg-aarch64: Support deposit
tcg-aarch64: Support add2, sub2
tcg-aarch64: Support muluh, mulsh
tcg-aarch64: Support div, rem
tcg-aarch64: Introduce tcg_out_insn_3405
tcg/aarch64/tcg-target.c | 801 +++++++++++++++++++++++++++++++++--------------
tcg/aarch64/tcg-target.h | 48 +--
2 files changed, 594 insertions(+), 255 deletions(-)
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Qemu-devel] [PULL 01/14] tcg-aarch64: Introduce tcg_out_insn
2014-03-14 20:09 [Qemu-devel] [PULL 00/14] tcg/aarch64 improvements, part 2 Richard Henderson
@ 2014-03-14 20:09 ` Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 02/14] tcg-aarch64: Convert shift insns to tcg_out_insn Richard Henderson
` (13 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2014-03-14 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, aliguori
Converting the add/sub (3.5.2) and logical shifted (3.5.10) instruction
groups to the new scheme.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
Tested-by: Claudio Fontana <claudio.fontana@huawei.com>
---
tcg/aarch64/tcg-target.c | 94 +++++++++++++++++++++++++++++-------------------
1 file changed, 58 insertions(+), 36 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index f43eb67..7cfe708 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -203,16 +203,27 @@ enum aarch64_ldst_op_type { /* type of operation */
LDST_LD_S_W = 0xc, /* load and sign-extend into Wt */
};
-enum aarch64_arith_opc {
- ARITH_AND = 0x0a,
- ARITH_ADD = 0x0b,
- ARITH_OR = 0x2a,
- ARITH_ADDS = 0x2b,
- ARITH_XOR = 0x4a,
- ARITH_SUB = 0x4b,
- ARITH_ANDS = 0x6a,
- ARITH_SUBS = 0x6b,
-};
+/* We encode the format of the insn into the beginning of the name, so that
+ we can have the preprocessor help "typecheck" the insn vs the output
+ function. Arm didn't provide us with nice names for the formats, so we
+ use the section number of the architecture reference manual in which the
+ instruction group is described. */
+typedef enum {
+ /* Add/subtract shifted register instructions (without a shift). */
+ I3502_ADD = 0x0b000000,
+ I3502_ADDS = 0x2b000000,
+ I3502_SUB = 0x4b000000,
+ I3502_SUBS = 0x6b000000,
+
+ /* Add/subtract shifted register instructions (with a shift). */
+ I3502S_ADD_LSL = I3502_ADD,
+
+ /* Logical shifted register instructions (without a shift). */
+ I3510_AND = 0x0a000000,
+ I3510_ORR = 0x2a000000,
+ I3510_EOR = 0x4a000000,
+ I3510_ANDS = 0x6a000000,
+} AArch64Insn;
enum aarch64_srr_opc {
SRR_SHL = 0x0,
@@ -299,6 +310,34 @@ static inline uint32_t tcg_in32(TCGContext *s)
return v;
}
+/* Emit an opcode with "type-checking" of the format. */
+#define tcg_out_insn(S, FMT, OP, ...) \
+ glue(tcg_out_insn_,FMT)(S, glue(glue(glue(I,FMT),_),OP), ## __VA_ARGS__)
+
+/* This function is for both 3.5.2 (Add/Subtract shifted register), for
+ the rare occasion when we actually want to supply a shift amount. */
+static inline void tcg_out_insn_3502S(TCGContext *s, AArch64Insn insn,
+ TCGType ext, TCGReg rd, TCGReg rn,
+ TCGReg rm, int imm6)
+{
+ tcg_out32(s, insn | ext << 31 | rm << 16 | imm6 << 10 | rn << 5 | rd);
+}
+
+/* This function is for 3.5.2 (Add/subtract shifted register),
+ and 3.5.10 (Logical shifted register), for the vast majorty of cases
+ when we don't want to apply a shift. Thus it can also be used for
+ 3.5.3 (Add/subtract with carry) and 3.5.8 (Data processing 2 source). */
+static void tcg_out_insn_3502(TCGContext *s, AArch64Insn insn, TCGType ext,
+ TCGReg rd, TCGReg rn, TCGReg rm)
+{
+ tcg_out32(s, insn | ext << 31 | rm << 16 | rn << 5 | rd);
+}
+
+#define tcg_out_insn_3503 tcg_out_insn_3502
+#define tcg_out_insn_3508 tcg_out_insn_3502
+#define tcg_out_insn_3510 tcg_out_insn_3502
+
+
static inline void tcg_out_ldst_9(TCGContext *s,
enum aarch64_ldst_op_data op_data,
enum aarch64_ldst_op_type op_type,
@@ -432,23 +471,6 @@ static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
arg, arg1, arg2);
}
-static inline void tcg_out_arith(TCGContext *s, enum aarch64_arith_opc opc,
- TCGType ext, TCGReg rd, TCGReg rn, TCGReg rm,
- int shift_imm)
-{
- /* Using shifted register arithmetic operations */
- /* if extended register operation (64bit) just OR with 0x80 << 24 */
- unsigned int shift, base = ext ? (0x80 | opc) << 24 : opc << 24;
- if (shift_imm == 0) {
- shift = 0;
- } else if (shift_imm > 0) {
- shift = shift_imm << 10 | 1 << 22;
- } else /* (shift_imm < 0) */ {
- shift = (-shift_imm) << 10;
- }
- tcg_out32(s, base | rm << 16 | shift | rn << 5 | rd);
-}
-
static inline void tcg_out_mul(TCGContext *s, TCGType ext,
TCGReg rd, TCGReg rn, TCGReg rm)
{
@@ -532,7 +554,7 @@ static inline void tcg_out_rotl(TCGContext *s, TCGType ext,
static void tcg_out_cmp(TCGContext *s, TCGType ext, TCGReg rn, TCGReg rm)
{
/* Using CMP alias SUBS wzr, Wn, Wm */
- tcg_out_arith(s, ARITH_SUBS, ext, TCG_REG_XZR, rn, rm, 0);
+ tcg_out_insn(s, 3502, SUBS, ext, TCG_REG_XZR, rn, rm);
}
static inline void tcg_out_cset(TCGContext *s, TCGType ext,
@@ -864,8 +886,8 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg,
tcg_out_addi(s, 1, TCG_REG_X2, base, tlb_offset & 0xfff000);
/* Merge the tlb index contribution into X2.
X2 = X2 + (X0 << CPU_TLB_ENTRY_BITS) */
- tcg_out_arith(s, ARITH_ADD, 1, TCG_REG_X2, TCG_REG_X2,
- TCG_REG_X0, -CPU_TLB_ENTRY_BITS);
+ tcg_out_insn(s, 3502S, ADD_LSL, 1, TCG_REG_X2, TCG_REG_X2,
+ TCG_REG_X0, CPU_TLB_ENTRY_BITS);
/* Merge "low bits" from tlb offset, load the tlb comparator into X0.
X0 = load [X2 + (tlb_offset & 0x000fff)] */
tcg_out_ldst(s, TARGET_LONG_BITS == 64 ? LDST_64 : LDST_32,
@@ -1141,27 +1163,27 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_add_i64:
case INDEX_op_add_i32:
- tcg_out_arith(s, ARITH_ADD, ext, a0, a1, a2, 0);
+ tcg_out_insn(s, 3502, ADD, ext, a0, a1, a2);
break;
case INDEX_op_sub_i64:
case INDEX_op_sub_i32:
- tcg_out_arith(s, ARITH_SUB, ext, a0, a1, a2, 0);
+ tcg_out_insn(s, 3502, SUB, ext, a0, a1, a2);
break;
case INDEX_op_and_i64:
case INDEX_op_and_i32:
- tcg_out_arith(s, ARITH_AND, ext, a0, a1, a2, 0);
+ tcg_out_insn(s, 3510, AND, ext, a0, a1, a2);
break;
case INDEX_op_or_i64:
case INDEX_op_or_i32:
- tcg_out_arith(s, ARITH_OR, ext, a0, a1, a2, 0);
+ tcg_out_insn(s, 3510, ORR, ext, a0, a1, a2);
break;
case INDEX_op_xor_i64:
case INDEX_op_xor_i32:
- tcg_out_arith(s, ARITH_XOR, ext, a0, a1, a2, 0);
+ tcg_out_insn(s, 3510, EOR, ext, a0, a1, a2);
break;
case INDEX_op_mul_i64:
@@ -1210,7 +1232,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
if (c2) { /* ROR / EXTR Wd, Wm, Wm, 32 - m */
tcg_out_rotl(s, ext, a0, a1, a2);
} else {
- tcg_out_arith(s, ARITH_SUB, 0, TCG_REG_TMP, TCG_REG_XZR, a2, 0);
+ tcg_out_insn(s, 3502, SUB, 0, TCG_REG_TMP, TCG_REG_XZR, a2);
tcg_out_shiftrot_reg(s, SRR_ROR, ext, a0, a1, TCG_REG_TMP);
}
break;
--
1.8.5.3
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PULL 02/14] tcg-aarch64: Convert shift insns to tcg_out_insn
2014-03-14 20:09 [Qemu-devel] [PULL 00/14] tcg/aarch64 improvements, part 2 Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 01/14] tcg-aarch64: Introduce tcg_out_insn Richard Henderson
@ 2014-03-14 20:09 ` Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 03/14] tcg-aarch64: Introduce tcg_out_insn_3401 Richard Henderson
` (12 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2014-03-14 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, aliguori
Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
Tested-by: Claudio Fontana <claudio.fontana@huawei.com>
---
tcg/aarch64/tcg-target.c | 52 +++++++++++++++++++-----------------------------
1 file changed, 21 insertions(+), 31 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 7cfe708..b52519e 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -218,6 +218,12 @@ typedef enum {
/* Add/subtract shifted register instructions (with a shift). */
I3502S_ADD_LSL = I3502_ADD,
+ /* Data-processing (2 source) instructions. */
+ I3508_LSLV = 0x1ac02000,
+ I3508_LSRV = 0x1ac02400,
+ I3508_ASRV = 0x1ac02800,
+ I3508_RORV = 0x1ac02c00,
+
/* Logical shifted register instructions (without a shift). */
I3510_AND = 0x0a000000,
I3510_ORR = 0x2a000000,
@@ -225,13 +231,6 @@ typedef enum {
I3510_ANDS = 0x6a000000,
} AArch64Insn;
-enum aarch64_srr_opc {
- SRR_SHL = 0x0,
- SRR_SHR = 0x4,
- SRR_SAR = 0x8,
- SRR_ROR = 0xc
-};
-
static inline enum aarch64_ldst_op_data
aarch64_ldst_get_data(TCGOpcode tcg_op)
{
@@ -479,15 +478,6 @@ static inline void tcg_out_mul(TCGContext *s, TCGType ext,
tcg_out32(s, base | rm << 16 | rn << 5 | rd);
}
-static inline void tcg_out_shiftrot_reg(TCGContext *s,
- enum aarch64_srr_opc opc, TCGType ext,
- TCGReg rd, TCGReg rn, TCGReg rm)
-{
- /* using 2-source data processing instructions 0x1ac02000 */
- unsigned int base = ext ? 0x9ac02000 : 0x1ac02000;
- tcg_out32(s, base | rm << 16 | opc << 8 | rn << 5 | rd);
-}
-
static inline void tcg_out_ubfm(TCGContext *s, TCGType ext, TCGReg rd,
TCGReg rn, unsigned int a, unsigned int b)
{
@@ -1193,47 +1183,47 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_shl_i64:
case INDEX_op_shl_i32:
- if (c2) { /* LSL / UBFM Wd, Wn, (32 - m) */
+ if (c2) {
tcg_out_shl(s, ext, a0, a1, a2);
- } else { /* LSL / LSLV */
- tcg_out_shiftrot_reg(s, SRR_SHL, ext, a0, a1, a2);
+ } else {
+ tcg_out_insn(s, 3508, LSLV, ext, a0, a1, a2);
}
break;
case INDEX_op_shr_i64:
case INDEX_op_shr_i32:
- if (c2) { /* LSR / UBFM Wd, Wn, m, 31 */
+ if (c2) {
tcg_out_shr(s, ext, a0, a1, a2);
- } else { /* LSR / LSRV */
- tcg_out_shiftrot_reg(s, SRR_SHR, ext, a0, a1, a2);
+ } else {
+ tcg_out_insn(s, 3508, LSRV, ext, a0, a1, a2);
}
break;
case INDEX_op_sar_i64:
case INDEX_op_sar_i32:
- if (c2) { /* ASR / SBFM Wd, Wn, m, 31 */
+ if (c2) {
tcg_out_sar(s, ext, a0, a1, a2);
- } else { /* ASR / ASRV */
- tcg_out_shiftrot_reg(s, SRR_SAR, ext, a0, a1, a2);
+ } else {
+ tcg_out_insn(s, 3508, ASRV, ext, a0, a1, a2);
}
break;
case INDEX_op_rotr_i64:
case INDEX_op_rotr_i32:
- if (c2) { /* ROR / EXTR Wd, Wm, Wm, m */
+ if (c2) {
tcg_out_rotr(s, ext, a0, a1, a2);
- } else { /* ROR / RORV */
- tcg_out_shiftrot_reg(s, SRR_ROR, ext, a0, a1, a2);
+ } else {
+ tcg_out_insn(s, 3508, RORV, ext, a0, a1, a2);
}
break;
case INDEX_op_rotl_i64:
- case INDEX_op_rotl_i32: /* same as rotate right by (32 - m) */
- if (c2) { /* ROR / EXTR Wd, Wm, Wm, 32 - m */
+ case INDEX_op_rotl_i32:
+ if (c2) {
tcg_out_rotl(s, ext, a0, a1, a2);
} else {
tcg_out_insn(s, 3502, SUB, 0, TCG_REG_TMP, TCG_REG_XZR, a2);
- tcg_out_shiftrot_reg(s, SRR_ROR, ext, a0, a1, TCG_REG_TMP);
+ tcg_out_insn(s, 3508, RORV, ext, a0, a1, TCG_REG_TMP);
}
break;
--
1.8.5.3
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PULL 03/14] tcg-aarch64: Introduce tcg_out_insn_3401
2014-03-14 20:09 [Qemu-devel] [PULL 00/14] tcg/aarch64 improvements, part 2 Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 01/14] tcg-aarch64: Introduce tcg_out_insn Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 02/14] tcg-aarch64: Convert shift insns to tcg_out_insn Richard Henderson
@ 2014-03-14 20:09 ` Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 04/14] tcg-aarch64: Implement mov with tcg_out_insn Richard Henderson
` (11 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2014-03-14 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, aliguori
This merges the implementation of tcg_out_addi and tcg_out_subi.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
Tested-by: Claudio Fontana <claudio.fontana@huawei.com>
---
tcg/aarch64/tcg-target.c | 72 +++++++++++++++++-------------------------------
1 file changed, 26 insertions(+), 46 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index b52519e..b5f19ad 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -209,6 +209,12 @@ enum aarch64_ldst_op_type { /* type of operation */
use the section number of the architecture reference manual in which the
instruction group is described. */
typedef enum {
+ /* Add/subtract immediate instructions. */
+ I3401_ADDI = 0x11000000,
+ I3401_ADDSI = 0x31000000,
+ I3401_SUBI = 0x51000000,
+ I3401_SUBSI = 0x71000000,
+
/* Add/subtract shifted register instructions (without a shift). */
I3502_ADD = 0x0b000000,
I3502_ADDS = 0x2b000000,
@@ -313,6 +319,18 @@ static inline uint32_t tcg_in32(TCGContext *s)
#define tcg_out_insn(S, FMT, OP, ...) \
glue(tcg_out_insn_,FMT)(S, glue(glue(glue(I,FMT),_),OP), ## __VA_ARGS__)
+static void tcg_out_insn_3401(TCGContext *s, AArch64Insn insn, TCGType ext,
+ TCGReg rd, TCGReg rn, uint64_t aimm)
+{
+ if (aimm > 0xfff) {
+ assert((aimm & 0xfff) == 0);
+ aimm >>= 12;
+ assert(aimm <= 0xfff);
+ aimm |= 1 << 12; /* apply LSL 12 */
+ }
+ tcg_out32(s, insn | ext << 31 | aimm << 10 | rn << 5 | rd);
+}
+
/* This function is for both 3.5.2 (Add/Subtract shifted register), for
the rare occasion when we actually want to supply a shift amount. */
static inline void tcg_out_insn_3502S(TCGContext *s, AArch64Insn insn,
@@ -736,46 +754,6 @@ static inline void tcg_out_uxt(TCGContext *s, int s_bits,
tcg_out_ubfm(s, 0, rd, rn, 0, bits);
}
-static inline void tcg_out_addi(TCGContext *s, TCGType ext,
- TCGReg rd, TCGReg rn, unsigned int aimm)
-{
- /* add immediate aimm unsigned 12bit value (with LSL 0 or 12) */
- /* using ADD 0x11000000 | (ext) | (aimm << 10) | (rn << 5) | rd */
- unsigned int base = ext ? 0x91000000 : 0x11000000;
-
- if (aimm <= 0xfff) {
- aimm <<= 10;
- } else {
- /* we can only shift left by 12, on assert we cannot represent */
- assert(!(aimm & 0xfff));
- assert(aimm <= 0xfff000);
- base |= 1 << 22; /* apply LSL 12 */
- aimm >>= 2;
- }
-
- tcg_out32(s, base | aimm | (rn << 5) | rd);
-}
-
-static inline void tcg_out_subi(TCGContext *s, TCGType ext,
- TCGReg rd, TCGReg rn, unsigned int aimm)
-{
- /* sub immediate aimm unsigned 12bit value (with LSL 0 or 12) */
- /* using SUB 0x51000000 | (ext) | (aimm << 10) | (rn << 5) | rd */
- unsigned int base = ext ? 0xd1000000 : 0x51000000;
-
- if (aimm <= 0xfff) {
- aimm <<= 10;
- } else {
- /* we can only shift left by 12, on assert we cannot represent */
- assert(!(aimm & 0xfff));
- assert(aimm <= 0xfff000);
- base |= 1 << 22; /* apply LSL 12 */
- aimm >>= 2;
- }
-
- tcg_out32(s, base | aimm | (rn << 5) | rd);
-}
-
#ifdef CONFIG_SOFTMMU
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
* int mmu_idx, uintptr_t ra)
@@ -871,9 +849,10 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg,
(TARGET_LONG_BITS - TARGET_PAGE_BITS) + s_bits,
(TARGET_LONG_BITS - TARGET_PAGE_BITS));
/* Add any "high bits" from the tlb offset to the env address into X2,
- to take advantage of the LSL12 form of the addi instruction.
+ to take advantage of the LSL12 form of the ADDI instruction.
X2 = env + (tlb_offset & 0xfff000) */
- tcg_out_addi(s, 1, TCG_REG_X2, base, tlb_offset & 0xfff000);
+ tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, TCG_REG_X2, base,
+ tlb_offset & 0xfff000);
/* Merge the tlb index contribution into X2.
X2 = X2 + (X0 << CPU_TLB_ENTRY_BITS) */
tcg_out_insn(s, 3502S, ADD_LSL, 1, TCG_REG_X2, TCG_REG_X2,
@@ -1476,9 +1455,10 @@ static void tcg_target_qemu_prologue(TCGContext *s)
tcg_out_store_pair(s, TCG_REG_FP, r, r + 1, idx);
}
- /* make stack space for TCG locals */
- tcg_out_subi(s, 1, TCG_REG_SP, TCG_REG_SP,
+ /* Make stack space for TCG locals. */
+ tcg_out_insn(s, 3401, SUBI, TCG_TYPE_I64, TCG_REG_SP, TCG_REG_SP,
frame_size_tcg_locals * TCG_TARGET_STACK_ALIGN);
+
/* inform TCG about how to find TCG locals with register, offset, size */
tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE,
CPU_TEMP_BUF_NLONGS * sizeof(long));
@@ -1495,8 +1475,8 @@ static void tcg_target_qemu_prologue(TCGContext *s)
tb_ret_addr = s->code_ptr;
- /* remove TCG locals stack space */
- tcg_out_addi(s, 1, TCG_REG_SP, TCG_REG_SP,
+ /* Remove TCG locals stack space. */
+ tcg_out_insn(s, 3401, ADDI, TCG_TYPE_I64, TCG_REG_SP, TCG_REG_SP,
frame_size_tcg_locals * TCG_TARGET_STACK_ALIGN);
/* restore registers x19..x28.
--
1.8.5.3
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PULL 04/14] tcg-aarch64: Implement mov with tcg_out_insn
2014-03-14 20:09 [Qemu-devel] [PULL 00/14] tcg/aarch64 improvements, part 2 Richard Henderson
` (2 preceding siblings ...)
2014-03-14 20:09 ` [Qemu-devel] [PULL 03/14] tcg-aarch64: Introduce tcg_out_insn_3401 Richard Henderson
@ 2014-03-14 20:09 ` Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 05/14] tcg-aarch64: Handle constant operands to add, sub, and compare Richard Henderson
` (10 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2014-03-14 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, aliguori
Avoid the magic numbers in the current implementation.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
Tested-by: Claudio Fontana <claudio.fontana@huawei.com>
---
tcg/aarch64/tcg-target.c | 24 +++++++++---------------
1 file changed, 9 insertions(+), 15 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index b5f19ad..9b6374d 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -376,13 +376,16 @@ static inline void tcg_out_ldst_12(TCGContext *s,
| op_type << 20 | scaled_uimm << 10 | rn << 5 | rd);
}
-static inline void tcg_out_movr(TCGContext *s, TCGType ext,
- TCGReg rd, TCGReg src)
+/* Register to register move using ORR (shifted register with no shift). */
+static void tcg_out_movr(TCGContext *s, TCGType ext, TCGReg rd, TCGReg rm)
{
- /* register to register move using MOV (shifted register with no shift) */
- /* using MOV 0x2a0003e0 | (shift).. */
- unsigned int base = ext ? 0xaa0003e0 : 0x2a0003e0;
- tcg_out32(s, base | src << 16 | rd);
+ tcg_out_insn(s, 3510, ORR, ext, rd, TCG_REG_XZR, rm);
+}
+
+/* Register to register move using ADDI (move to/from SP). */
+static void tcg_out_movr_sp(TCGContext *s, TCGType ext, TCGReg rd, TCGReg rn)
+{
+ tcg_out_insn(s, 3401, ADDI, ext, rd, rn, 0);
}
static inline void tcg_out_movi_aux(TCGContext *s,
@@ -457,15 +460,6 @@ static inline void tcg_out_ldst(TCGContext *s, enum aarch64_ldst_op_data data,
tcg_out_ldst_r(s, data, type, rd, rn, TCG_REG_TMP);
}
-/* mov alias implemented with add immediate, useful to move to/from SP */
-static inline void tcg_out_movr_sp(TCGContext *s, TCGType ext,
- TCGReg rd, TCGReg rn)
-{
- /* using ADD 0x11000000 | (ext) | rn << 5 | rd */
- unsigned int base = ext ? 0x91000000 : 0x11000000;
- tcg_out32(s, base | rn << 5 | rd);
-}
-
static inline void tcg_out_mov(TCGContext *s,
TCGType type, TCGReg ret, TCGReg arg)
{
--
1.8.5.3
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PULL 05/14] tcg-aarch64: Handle constant operands to add, sub, and compare
2014-03-14 20:09 [Qemu-devel] [PULL 00/14] tcg/aarch64 improvements, part 2 Richard Henderson
` (3 preceding siblings ...)
2014-03-14 20:09 ` [Qemu-devel] [PULL 04/14] tcg-aarch64: Implement mov with tcg_out_insn Richard Henderson
@ 2014-03-14 20:09 ` Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 06/14] tcg-aarch64: Handle constant operands to and, or, xor Richard Henderson
` (9 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2014-03-14 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, aliguori
Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
Tested-by: Claudio Fontana <claudio.fontana@huawei.com>
---
tcg/aarch64/tcg-target.c | 100 ++++++++++++++++++++++++++++++++++++-----------
1 file changed, 78 insertions(+), 22 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 9b6374d..6816deb 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -110,6 +110,9 @@ static inline void patch_reloc(uint8_t *code_ptr, int type,
}
}
+#define TCG_CT_CONST_IS32 0x100
+#define TCG_CT_CONST_AIMM 0x200
+
/* parse target specific constraints */
static int target_parse_constraint(TCGArgConstraint *ct,
const char **pct_str)
@@ -133,6 +136,12 @@ static int target_parse_constraint(TCGArgConstraint *ct,
tcg_regset_reset_reg(ct->u.regs, TCG_REG_X3);
#endif
break;
+ case 'w': /* The operand should be considered 32-bit. */
+ ct->ct |= TCG_CT_CONST_IS32;
+ break;
+ case 'A': /* Valid for arithmetic immediate (positive or negative). */
+ ct->ct |= TCG_CT_CONST_AIMM;
+ break;
default:
return -1;
}
@@ -142,14 +151,25 @@ static int target_parse_constraint(TCGArgConstraint *ct,
return 0;
}
-static inline int tcg_target_const_match(tcg_target_long val,
- const TCGArgConstraint *arg_ct)
+static inline bool is_aimm(uint64_t val)
+{
+ return (val & ~0xfff) == 0 || (val & ~0xfff000) == 0;
+}
+
+static int tcg_target_const_match(tcg_target_long val,
+ const TCGArgConstraint *arg_ct)
{
int ct = arg_ct->ct;
if (ct & TCG_CT_CONST) {
return 1;
}
+ if (ct & TCG_CT_CONST_IS32) {
+ val = (int32_t)val;
+ }
+ if ((ct & TCG_CT_CONST_AIMM) && (is_aimm(val) || is_aimm(-val))) {
+ return 1;
+ }
return 0;
}
@@ -553,10 +573,20 @@ static inline void tcg_out_rotl(TCGContext *s, TCGType ext,
tcg_out_extr(s, ext, rd, rn, rn, bits - (m & max));
}
-static void tcg_out_cmp(TCGContext *s, TCGType ext, TCGReg rn, TCGReg rm)
+static void tcg_out_cmp(TCGContext *s, TCGType ext, TCGReg a,
+ tcg_target_long b, bool const_b)
{
- /* Using CMP alias SUBS wzr, Wn, Wm */
- tcg_out_insn(s, 3502, SUBS, ext, TCG_REG_XZR, rn, rm);
+ if (const_b) {
+ /* Using CMP or CMN aliases. */
+ if (b >= 0) {
+ tcg_out_insn(s, 3401, SUBSI, ext, TCG_REG_XZR, a, b);
+ } else {
+ tcg_out_insn(s, 3401, ADDSI, ext, TCG_REG_XZR, a, -b);
+ }
+ } else {
+ /* Using CMP alias SUBS wzr, Wn, Wm */
+ tcg_out_insn(s, 3502, SUBS, ext, TCG_REG_XZR, a, b);
+ }
}
static inline void tcg_out_cset(TCGContext *s, TCGType ext,
@@ -748,6 +778,16 @@ static inline void tcg_out_uxt(TCGContext *s, int s_bits,
tcg_out_ubfm(s, 0, rd, rn, 0, bits);
}
+static void tcg_out_addsubi(TCGContext *s, int ext, TCGReg rd,
+ TCGReg rn, int64_t aimm)
+{
+ if (aimm >= 0) {
+ tcg_out_insn(s, 3401, ADDI, ext, rd, rn, aimm);
+ } else {
+ tcg_out_insn(s, 3401, SUBI, ext, rd, rn, -aimm);
+ }
+}
+
#ifdef CONFIG_SOFTMMU
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
* int mmu_idx, uintptr_t ra)
@@ -863,7 +903,7 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg,
(is_read ? offsetof(CPUTLBEntry, addr_read)
: offsetof(CPUTLBEntry, addr_write)));
/* Perform the address comparison. */
- tcg_out_cmp(s, (TARGET_LONG_BITS == 64), TCG_REG_X0, TCG_REG_X3);
+ tcg_out_cmp(s, (TARGET_LONG_BITS == 64), TCG_REG_X0, TCG_REG_X3, 0);
*label_ptr = s->code_ptr;
/* If not equal, we jump to the slow path. */
tcg_out_goto_cond_noaddr(s, TCG_COND_NE);
@@ -1124,14 +1164,26 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
a0, a1, a2);
break;
- case INDEX_op_add_i64:
case INDEX_op_add_i32:
- tcg_out_insn(s, 3502, ADD, ext, a0, a1, a2);
+ a2 = (int32_t)a2;
+ /* FALLTHRU */
+ case INDEX_op_add_i64:
+ if (c2) {
+ tcg_out_addsubi(s, ext, a0, a1, a2);
+ } else {
+ tcg_out_insn(s, 3502, ADD, ext, a0, a1, a2);
+ }
break;
- case INDEX_op_sub_i64:
case INDEX_op_sub_i32:
- tcg_out_insn(s, 3502, SUB, ext, a0, a1, a2);
+ a2 = (int32_t)a2;
+ /* FALLTHRU */
+ case INDEX_op_sub_i64:
+ if (c2) {
+ tcg_out_addsubi(s, ext, a0, a1, -a2);
+ } else {
+ tcg_out_insn(s, 3502, SUB, ext, a0, a1, a2);
+ }
break;
case INDEX_op_and_i64:
@@ -1200,15 +1252,19 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
break;
- case INDEX_op_brcond_i64:
case INDEX_op_brcond_i32:
- tcg_out_cmp(s, ext, a0, a1);
+ a1 = (int32_t)a1;
+ /* FALLTHRU */
+ case INDEX_op_brcond_i64:
+ tcg_out_cmp(s, ext, a0, a1, const_args[1]);
tcg_out_goto_label_cond(s, a2, args[3]);
break;
- case INDEX_op_setcond_i64:
case INDEX_op_setcond_i32:
- tcg_out_cmp(s, ext, a1, a2);
+ a2 = (int32_t)a2;
+ /* FALLTHRU */
+ case INDEX_op_setcond_i64:
+ tcg_out_cmp(s, ext, a1, a2, c2);
tcg_out_cset(s, 0, a0, args[3]);
break;
@@ -1329,10 +1385,10 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
{ INDEX_op_st32_i64, { "r", "r" } },
{ INDEX_op_st_i64, { "r", "r" } },
- { INDEX_op_add_i32, { "r", "r", "r" } },
- { INDEX_op_add_i64, { "r", "r", "r" } },
- { INDEX_op_sub_i32, { "r", "r", "r" } },
- { INDEX_op_sub_i64, { "r", "r", "r" } },
+ { INDEX_op_add_i32, { "r", "r", "rwA" } },
+ { INDEX_op_add_i64, { "r", "r", "rA" } },
+ { INDEX_op_sub_i32, { "r", "r", "rwA" } },
+ { INDEX_op_sub_i64, { "r", "r", "rA" } },
{ INDEX_op_mul_i32, { "r", "r", "r" } },
{ INDEX_op_mul_i64, { "r", "r", "r" } },
{ INDEX_op_and_i32, { "r", "r", "r" } },
@@ -1353,10 +1409,10 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
{ INDEX_op_rotl_i64, { "r", "r", "ri" } },
{ INDEX_op_rotr_i64, { "r", "r", "ri" } },
- { INDEX_op_brcond_i32, { "r", "r" } },
- { INDEX_op_setcond_i32, { "r", "r", "r" } },
- { INDEX_op_brcond_i64, { "r", "r" } },
- { INDEX_op_setcond_i64, { "r", "r", "r" } },
+ { INDEX_op_brcond_i32, { "r", "rwA" } },
+ { INDEX_op_brcond_i64, { "r", "rA" } },
+ { INDEX_op_setcond_i32, { "r", "r", "rwA" } },
+ { INDEX_op_setcond_i64, { "r", "r", "rA" } },
{ INDEX_op_qemu_ld8u, { "r", "l" } },
{ INDEX_op_qemu_ld8s, { "r", "l" } },
--
1.8.5.3
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PULL 06/14] tcg-aarch64: Handle constant operands to and, or, xor
2014-03-14 20:09 [Qemu-devel] [PULL 00/14] tcg/aarch64 improvements, part 2 Richard Henderson
` (4 preceding siblings ...)
2014-03-14 20:09 ` [Qemu-devel] [PULL 05/14] tcg-aarch64: Handle constant operands to add, sub, and compare Richard Henderson
@ 2014-03-14 20:09 ` Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 07/14] tcg-aarch64: Support andc, orc, eqv, not, neg Richard Henderson
` (8 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2014-03-14 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, aliguori
Handle a simplified set of logical immediates for the moment.
The way gcc and binutils do it, with 52k worth of tables, and
a binary search depth of log2(5334) = 13, seems slow for the
most common cases.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
Tested-by: Claudio Fontana <claudio.fontana@huawei.com>
---
tcg/aarch64/tcg-target.c | 156 ++++++++++++++++++++++++++++++++---------------
1 file changed, 107 insertions(+), 49 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 6816deb..9a34a15 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -112,6 +112,7 @@ static inline void patch_reloc(uint8_t *code_ptr, int type,
#define TCG_CT_CONST_IS32 0x100
#define TCG_CT_CONST_AIMM 0x200
+#define TCG_CT_CONST_LIMM 0x400
/* parse target specific constraints */
static int target_parse_constraint(TCGArgConstraint *ct,
@@ -142,6 +143,9 @@ static int target_parse_constraint(TCGArgConstraint *ct,
case 'A': /* Valid for arithmetic immediate (positive or negative). */
ct->ct |= TCG_CT_CONST_AIMM;
break;
+ case 'L': /* Valid for logical immediate. */
+ ct->ct |= TCG_CT_CONST_LIMM;
+ break;
default:
return -1;
}
@@ -156,6 +160,26 @@ static inline bool is_aimm(uint64_t val)
return (val & ~0xfff) == 0 || (val & ~0xfff000) == 0;
}
+static inline bool is_limm(uint64_t val)
+{
+ /* Taking a simplified view of the logical immediates for now, ignoring
+ the replication that can happen across the field. Match bit patterns
+ of the forms
+ 0....01....1
+ 0..01..10..0
+ and their inverses. */
+
+ /* Make things easier below, by testing the form with msb clear. */
+ if ((int64_t)val < 0) {
+ val = ~val;
+ }
+ if (val == 0) {
+ return false;
+ }
+ val += val & -val;
+ return (val & (val - 1)) == 0;
+}
+
static int tcg_target_const_match(tcg_target_long val,
const TCGArgConstraint *arg_ct)
{
@@ -170,6 +194,9 @@ static int tcg_target_const_match(tcg_target_long val,
if ((ct & TCG_CT_CONST_AIMM) && (is_aimm(val) || is_aimm(-val))) {
return 1;
}
+ if ((ct & TCG_CT_CONST_LIMM) && is_limm(val)) {
+ return 1;
+ }
return 0;
}
@@ -235,6 +262,11 @@ typedef enum {
I3401_SUBI = 0x51000000,
I3401_SUBSI = 0x71000000,
+ /* Logical immediate instructions. */
+ I3404_ANDI = 0x12000000,
+ I3404_ORRI = 0x32000000,
+ I3404_EORI = 0x52000000,
+
/* Add/subtract shifted register instructions (without a shift). */
I3502_ADD = 0x0b000000,
I3502_ADDS = 0x2b000000,
@@ -351,6 +383,18 @@ static void tcg_out_insn_3401(TCGContext *s, AArch64Insn insn, TCGType ext,
tcg_out32(s, insn | ext << 31 | aimm << 10 | rn << 5 | rd);
}
+/* This function can be used for both 3.4.2 (Bitfield) and 3.4.4
+ (Logical immediate). Both insn groups have N, IMMR and IMMS fields
+ that feed the DecodeBitMasks pseudo function. */
+static void tcg_out_insn_3402(TCGContext *s, AArch64Insn insn, TCGType ext,
+ TCGReg rd, TCGReg rn, int n, int immr, int imms)
+{
+ tcg_out32(s, insn | ext << 31 | n << 22 | immr << 16 | imms << 10
+ | rn << 5 | rd);
+}
+
+#define tcg_out_insn_3404 tcg_out_insn_3402
+
/* This function is for both 3.5.2 (Add/Subtract shifted register), for
the rare occasion when we actually want to supply a shift amount. */
static inline void tcg_out_insn_3502S(TCGContext *s, AArch64Insn insn,
@@ -665,40 +709,6 @@ static inline void tcg_out_call(TCGContext *s, intptr_t target)
}
}
-/* encode a logical immediate, mapping user parameter
- M=set bits pattern length to S=M-1 */
-static inline unsigned int
-aarch64_limm(unsigned int m, unsigned int r)
-{
- assert(m > 0);
- return r << 16 | (m - 1) << 10;
-}
-
-/* test a register against an immediate bit pattern made of
- M set bits rotated right by R.
- Examples:
- to test a 32/64 reg against 0x00000007, pass M = 3, R = 0.
- to test a 32/64 reg against 0x000000ff, pass M = 8, R = 0.
- to test a 32bit reg against 0xff000000, pass M = 8, R = 8.
- to test a 32bit reg against 0xff0000ff, pass M = 16, R = 8.
- */
-static inline void tcg_out_tst(TCGContext *s, TCGType ext, TCGReg rn,
- unsigned int m, unsigned int r)
-{
- /* using TST alias of ANDS XZR, Xn,#bimm64 0x7200001f */
- unsigned int base = ext ? 0xf240001f : 0x7200001f;
- tcg_out32(s, base | aarch64_limm(m, r) | rn << 5);
-}
-
-/* and a register with a bit pattern, similarly to TST, no flags change */
-static inline void tcg_out_andi(TCGContext *s, TCGType ext, TCGReg rd,
- TCGReg rn, unsigned int m, unsigned int r)
-{
- /* using AND 0x12000000 */
- unsigned int base = ext ? 0x92400000 : 0x12000000;
- tcg_out32(s, base | aarch64_limm(m, r) | rn << 5 | rd);
-}
-
static inline void tcg_out_ret(TCGContext *s)
{
/* emit RET { LR } */
@@ -788,6 +798,37 @@ static void tcg_out_addsubi(TCGContext *s, int ext, TCGReg rd,
}
}
+/* This function is used for the Logical (immediate) instruction group.
+ The value of LIMM must satisfy IS_LIMM. See the comment above about
+ only supporting simplified logical immediates. */
+static void tcg_out_logicali(TCGContext *s, AArch64Insn insn, TCGType ext,
+ TCGReg rd, TCGReg rn, uint64_t limm)
+{
+ unsigned h, l, r, c;
+
+ assert(is_limm(limm));
+
+ h = clz64(limm);
+ l = ctz64(limm);
+ if (l == 0) {
+ r = 0; /* form 0....01....1 */
+ c = ctz64(~limm) - 1;
+ if (h == 0) {
+ r = clz64(~limm); /* form 1..10..01..1 */
+ c += r;
+ }
+ } else {
+ r = 64 - l; /* form 1....10....0 or 0..01..10..0 */
+ c = r - h - 1;
+ }
+ if (ext == TCG_TYPE_I32) {
+ r &= 31;
+ c &= 31;
+ }
+
+ tcg_out_insn_3404(s, insn, ext, rd, rn, ext, r, c);
+}
+
#ifdef CONFIG_SOFTMMU
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
* int mmu_idx, uintptr_t ra)
@@ -879,9 +920,8 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg,
/* Store the page mask part of the address and the low s_bits into X3.
Later this allows checking for equality and alignment at the same time.
X3 = addr_reg & (PAGE_MASK | ((1 << s_bits) - 1)) */
- tcg_out_andi(s, (TARGET_LONG_BITS == 64), TCG_REG_X3, addr_reg,
- (TARGET_LONG_BITS - TARGET_PAGE_BITS) + s_bits,
- (TARGET_LONG_BITS - TARGET_PAGE_BITS));
+ tcg_out_logicali(s, I3404_ANDI, TARGET_LONG_BITS == 64, TCG_REG_X3,
+ addr_reg, TARGET_PAGE_MASK | ((1 << s_bits) - 1));
/* Add any "high bits" from the tlb offset to the env address into X2,
to take advantage of the LSL12 form of the ADDI instruction.
X2 = env + (tlb_offset & 0xfff000) */
@@ -1186,19 +1226,37 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
break;
- case INDEX_op_and_i64:
case INDEX_op_and_i32:
- tcg_out_insn(s, 3510, AND, ext, a0, a1, a2);
+ a2 = (int32_t)a2;
+ /* FALLTHRU */
+ case INDEX_op_and_i64:
+ if (c2) {
+ tcg_out_logicali(s, I3404_ANDI, ext, a0, a1, a2);
+ } else {
+ tcg_out_insn(s, 3510, AND, ext, a0, a1, a2);
+ }
break;
- case INDEX_op_or_i64:
case INDEX_op_or_i32:
- tcg_out_insn(s, 3510, ORR, ext, a0, a1, a2);
+ a2 = (int32_t)a2;
+ /* FALLTHRU */
+ case INDEX_op_or_i64:
+ if (c2) {
+ tcg_out_logicali(s, I3404_ORRI, ext, a0, a1, a2);
+ } else {
+ tcg_out_insn(s, 3510, ORR, ext, a0, a1, a2);
+ }
break;
- case INDEX_op_xor_i64:
case INDEX_op_xor_i32:
- tcg_out_insn(s, 3510, EOR, ext, a0, a1, a2);
+ a2 = (int32_t)a2;
+ /* FALLTHRU */
+ case INDEX_op_xor_i64:
+ if (c2) {
+ tcg_out_logicali(s, I3404_EORI, ext, a0, a1, a2);
+ } else {
+ tcg_out_insn(s, 3510, EOR, ext, a0, a1, a2);
+ }
break;
case INDEX_op_mul_i64:
@@ -1391,12 +1449,12 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
{ INDEX_op_sub_i64, { "r", "r", "rA" } },
{ INDEX_op_mul_i32, { "r", "r", "r" } },
{ INDEX_op_mul_i64, { "r", "r", "r" } },
- { INDEX_op_and_i32, { "r", "r", "r" } },
- { INDEX_op_and_i64, { "r", "r", "r" } },
- { INDEX_op_or_i32, { "r", "r", "r" } },
- { INDEX_op_or_i64, { "r", "r", "r" } },
- { INDEX_op_xor_i32, { "r", "r", "r" } },
- { INDEX_op_xor_i64, { "r", "r", "r" } },
+ { INDEX_op_and_i32, { "r", "r", "rwL" } },
+ { INDEX_op_and_i64, { "r", "r", "rL" } },
+ { INDEX_op_or_i32, { "r", "r", "rwL" } },
+ { INDEX_op_or_i64, { "r", "r", "rL" } },
+ { INDEX_op_xor_i32, { "r", "r", "rwL" } },
+ { INDEX_op_xor_i64, { "r", "r", "rL" } },
{ INDEX_op_shl_i32, { "r", "r", "ri" } },
{ INDEX_op_shr_i32, { "r", "r", "ri" } },
--
1.8.5.3
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PULL 07/14] tcg-aarch64: Support andc, orc, eqv, not, neg
2014-03-14 20:09 [Qemu-devel] [PULL 00/14] tcg/aarch64 improvements, part 2 Richard Henderson
` (5 preceding siblings ...)
2014-03-14 20:09 ` [Qemu-devel] [PULL 06/14] tcg-aarch64: Handle constant operands to and, or, xor Richard Henderson
@ 2014-03-14 20:09 ` Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 08/14] tcg-aarch64: Support movcond Richard Henderson
` (7 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2014-03-14 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, aliguori
Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
Tested-by: Claudio Fontana <claudio.fontana@huawei.com>
---
tcg/aarch64/tcg-target.c | 57 ++++++++++++++++++++++++++++++++++++++++++++++++
tcg/aarch64/tcg-target.h | 20 ++++++++---------
2 files changed, 67 insertions(+), 10 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 9a34a15..5850ae4 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -284,8 +284,11 @@ typedef enum {
/* Logical shifted register instructions (without a shift). */
I3510_AND = 0x0a000000,
+ I3510_BIC = 0x0a200000,
I3510_ORR = 0x2a000000,
+ I3510_ORN = 0x2a200000,
I3510_EOR = 0x4a000000,
+ I3510_EON = 0x4a200000,
I3510_ANDS = 0x6a000000,
} AArch64Insn;
@@ -1226,6 +1229,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
break;
+ case INDEX_op_neg_i64:
+ case INDEX_op_neg_i32:
+ tcg_out_insn(s, 3502, SUB, ext, a0, TCG_REG_XZR, a1);
+ break;
+
case INDEX_op_and_i32:
a2 = (int32_t)a2;
/* FALLTHRU */
@@ -1237,6 +1245,17 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
break;
+ case INDEX_op_andc_i32:
+ a2 = (int32_t)a2;
+ /* FALLTHRU */
+ case INDEX_op_andc_i64:
+ if (c2) {
+ tcg_out_logicali(s, I3404_ANDI, ext, a0, a1, ~a2);
+ } else {
+ tcg_out_insn(s, 3510, BIC, ext, a0, a1, a2);
+ }
+ break;
+
case INDEX_op_or_i32:
a2 = (int32_t)a2;
/* FALLTHRU */
@@ -1248,6 +1267,17 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
break;
+ case INDEX_op_orc_i32:
+ a2 = (int32_t)a2;
+ /* FALLTHRU */
+ case INDEX_op_orc_i64:
+ if (c2) {
+ tcg_out_logicali(s, I3404_ORRI, ext, a0, a1, ~a2);
+ } else {
+ tcg_out_insn(s, 3510, ORN, ext, a0, a1, a2);
+ }
+ break;
+
case INDEX_op_xor_i32:
a2 = (int32_t)a2;
/* FALLTHRU */
@@ -1259,6 +1289,22 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
}
break;
+ case INDEX_op_eqv_i32:
+ a2 = (int32_t)a2;
+ /* FALLTHRU */
+ case INDEX_op_eqv_i64:
+ if (c2) {
+ tcg_out_logicali(s, I3404_EORI, ext, a0, a1, ~a2);
+ } else {
+ tcg_out_insn(s, 3510, EON, ext, a0, a1, a2);
+ }
+ break;
+
+ case INDEX_op_not_i64:
+ case INDEX_op_not_i32:
+ tcg_out_insn(s, 3510, ORN, ext, a0, TCG_REG_XZR, a1);
+ break;
+
case INDEX_op_mul_i64:
case INDEX_op_mul_i32:
tcg_out_mul(s, ext, a0, a1, a2);
@@ -1455,6 +1501,17 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
{ INDEX_op_or_i64, { "r", "r", "rL" } },
{ INDEX_op_xor_i32, { "r", "r", "rwL" } },
{ INDEX_op_xor_i64, { "r", "r", "rL" } },
+ { INDEX_op_andc_i32, { "r", "r", "rwL" } },
+ { INDEX_op_andc_i64, { "r", "r", "rL" } },
+ { INDEX_op_orc_i32, { "r", "r", "rwL" } },
+ { INDEX_op_orc_i64, { "r", "r", "rL" } },
+ { INDEX_op_eqv_i32, { "r", "r", "rwL" } },
+ { INDEX_op_eqv_i64, { "r", "r", "rL" } },
+
+ { INDEX_op_neg_i32, { "r", "r" } },
+ { INDEX_op_neg_i64, { "r", "r" } },
+ { INDEX_op_not_i32, { "r", "r" } },
+ { INDEX_op_not_i64, { "r", "r" } },
{ INDEX_op_shl_i32, { "r", "r", "ri" } },
{ INDEX_op_shr_i32, { "r", "r", "ri" } },
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 82ad919..f2945b5 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -47,12 +47,12 @@ typedef enum {
#define TCG_TARGET_HAS_ext16u_i32 1
#define TCG_TARGET_HAS_bswap16_i32 1
#define TCG_TARGET_HAS_bswap32_i32 1
-#define TCG_TARGET_HAS_not_i32 0
-#define TCG_TARGET_HAS_neg_i32 0
+#define TCG_TARGET_HAS_not_i32 1
+#define TCG_TARGET_HAS_neg_i32 1
#define TCG_TARGET_HAS_rot_i32 1
-#define TCG_TARGET_HAS_andc_i32 0
-#define TCG_TARGET_HAS_orc_i32 0
-#define TCG_TARGET_HAS_eqv_i32 0
+#define TCG_TARGET_HAS_andc_i32 1
+#define TCG_TARGET_HAS_orc_i32 1
+#define TCG_TARGET_HAS_eqv_i32 1
#define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 0
#define TCG_TARGET_HAS_deposit_i32 0
@@ -75,12 +75,12 @@ typedef enum {
#define TCG_TARGET_HAS_bswap16_i64 1
#define TCG_TARGET_HAS_bswap32_i64 1
#define TCG_TARGET_HAS_bswap64_i64 1
-#define TCG_TARGET_HAS_not_i64 0
-#define TCG_TARGET_HAS_neg_i64 0
+#define TCG_TARGET_HAS_not_i64 1
+#define TCG_TARGET_HAS_neg_i64 1
#define TCG_TARGET_HAS_rot_i64 1
-#define TCG_TARGET_HAS_andc_i64 0
-#define TCG_TARGET_HAS_orc_i64 0
-#define TCG_TARGET_HAS_eqv_i64 0
+#define TCG_TARGET_HAS_andc_i64 1
+#define TCG_TARGET_HAS_orc_i64 1
+#define TCG_TARGET_HAS_eqv_i64 1
#define TCG_TARGET_HAS_nand_i64 0
#define TCG_TARGET_HAS_nor_i64 0
#define TCG_TARGET_HAS_deposit_i64 0
--
1.8.5.3
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PULL 08/14] tcg-aarch64: Support movcond
2014-03-14 20:09 [Qemu-devel] [PULL 00/14] tcg/aarch64 improvements, part 2 Richard Henderson
` (6 preceding siblings ...)
2014-03-14 20:09 ` [Qemu-devel] [PULL 07/14] tcg-aarch64: Support andc, orc, eqv, not, neg Richard Henderson
@ 2014-03-14 20:09 ` Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 09/14] tcg-aarch64: Use tcg_out_insn for setcond Richard Henderson
` (6 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2014-03-14 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, aliguori
Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
Tested-by: Claudio Fontana <claudio.fontana@huawei.com>
---
tcg/aarch64/tcg-target.c | 34 ++++++++++++++++++++++++++++++++++
tcg/aarch64/tcg-target.h | 4 ++--
2 files changed, 36 insertions(+), 2 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 5850ae4..7f41c75 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -113,6 +113,7 @@ static inline void patch_reloc(uint8_t *code_ptr, int type,
#define TCG_CT_CONST_IS32 0x100
#define TCG_CT_CONST_AIMM 0x200
#define TCG_CT_CONST_LIMM 0x400
+#define TCG_CT_CONST_ZERO 0x800
/* parse target specific constraints */
static int target_parse_constraint(TCGArgConstraint *ct,
@@ -146,6 +147,9 @@ static int target_parse_constraint(TCGArgConstraint *ct,
case 'L': /* Valid for logical immediate. */
ct->ct |= TCG_CT_CONST_LIMM;
break;
+ case 'Z': /* zero */
+ ct->ct |= TCG_CT_CONST_ZERO;
+ break;
default:
return -1;
}
@@ -197,6 +201,9 @@ static int tcg_target_const_match(tcg_target_long val,
if ((ct & TCG_CT_CONST_LIMM) && is_limm(val)) {
return 1;
}
+ if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
+ return 1;
+ }
return 0;
}
@@ -276,6 +283,10 @@ typedef enum {
/* Add/subtract shifted register instructions (with a shift). */
I3502S_ADD_LSL = I3502_ADD,
+ /* Conditional select instructions. */
+ I3506_CSEL = 0x1a800000,
+ I3506_CSINC = 0x1a800400,
+
/* Data-processing (2 source) instructions. */
I3508_LSLV = 0x1ac02000,
I3508_LSRV = 0x1ac02400,
@@ -421,6 +432,13 @@ static void tcg_out_insn_3502(TCGContext *s, AArch64Insn insn, TCGType ext,
#define tcg_out_insn_3508 tcg_out_insn_3502
#define tcg_out_insn_3510 tcg_out_insn_3502
+static void tcg_out_insn_3506(TCGContext *s, AArch64Insn insn, TCGType ext,
+ TCGReg rd, TCGReg rn, TCGReg rm, TCGCond c)
+{
+ tcg_out32(s, insn | ext << 31 | rm << 16 | rn << 5 | rd
+ | tcg_cond_to_aarch64[c] << 12);
+}
+
static inline void tcg_out_ldst_9(TCGContext *s,
enum aarch64_ldst_op_data op_data,
@@ -1154,6 +1172,10 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
TCGArg a2 = args[2];
int c2 = const_args[2];
+ /* Some operands are defined with "rZ" constraint, a register or
+ the zero register. These need not actually test args[I] == 0. */
+#define REG0(I) (const_args[I] ? TCG_REG_XZR : (TCGReg)args[I])
+
switch (opc) {
case INDEX_op_exit_tb:
tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_X0, a0);
@@ -1372,6 +1394,14 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_cset(s, 0, a0, args[3]);
break;
+ case INDEX_op_movcond_i32:
+ a2 = (int32_t)a2;
+ /* FALLTHRU */
+ case INDEX_op_movcond_i64:
+ tcg_out_cmp(s, ext, a1, a2, c2);
+ tcg_out_insn(s, 3506, CSEL, ext, a0, REG0(3), REG0(4), args[5]);
+ break;
+
case INDEX_op_qemu_ld8u:
tcg_out_qemu_ld(s, args, 0 | 0);
break;
@@ -1454,6 +1484,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
/* Opcode not implemented. */
tcg_abort();
}
+
+#undef REG0
}
static const TCGTargetOpDef aarch64_op_defs[] = {
@@ -1528,6 +1560,8 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
{ INDEX_op_brcond_i64, { "r", "rA" } },
{ INDEX_op_setcond_i32, { "r", "r", "rwA" } },
{ INDEX_op_setcond_i64, { "r", "r", "rA" } },
+ { INDEX_op_movcond_i32, { "r", "r", "rwA", "rZ", "rZ" } },
+ { INDEX_op_movcond_i64, { "r", "r", "rA", "rZ", "rZ" } },
{ INDEX_op_qemu_ld8u, { "r", "l" } },
{ INDEX_op_qemu_ld8s, { "r", "l" } },
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index f2945b5..862600a 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -56,7 +56,7 @@ typedef enum {
#define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 0
#define TCG_TARGET_HAS_deposit_i32 0
-#define TCG_TARGET_HAS_movcond_i32 0
+#define TCG_TARGET_HAS_movcond_i32 1
#define TCG_TARGET_HAS_add2_i32 0
#define TCG_TARGET_HAS_sub2_i32 0
#define TCG_TARGET_HAS_mulu2_i32 0
@@ -84,7 +84,7 @@ typedef enum {
#define TCG_TARGET_HAS_nand_i64 0
#define TCG_TARGET_HAS_nor_i64 0
#define TCG_TARGET_HAS_deposit_i64 0
-#define TCG_TARGET_HAS_movcond_i64 0
+#define TCG_TARGET_HAS_movcond_i64 1
#define TCG_TARGET_HAS_add2_i64 0
#define TCG_TARGET_HAS_sub2_i64 0
#define TCG_TARGET_HAS_mulu2_i64 0
--
1.8.5.3
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PULL 09/14] tcg-aarch64: Use tcg_out_insn for setcond
2014-03-14 20:09 [Qemu-devel] [PULL 00/14] tcg/aarch64 improvements, part 2 Richard Henderson
` (7 preceding siblings ...)
2014-03-14 20:09 ` [Qemu-devel] [PULL 08/14] tcg-aarch64: Support movcond Richard Henderson
@ 2014-03-14 20:09 ` Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 10/14] tcg-aarch64: Support deposit Richard Henderson
` (5 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2014-03-14 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, aliguori
Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
Tested-by: Claudio Fontana <claudio.fontana@huawei.com>
---
tcg/aarch64/tcg-target.c | 12 +++---------
1 file changed, 3 insertions(+), 9 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 7f41c75..c38e3c0 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -654,14 +654,6 @@ static void tcg_out_cmp(TCGContext *s, TCGType ext, TCGReg a,
}
}
-static inline void tcg_out_cset(TCGContext *s, TCGType ext,
- TCGReg rd, TCGCond c)
-{
- /* Using CSET alias of CSINC 0x1a800400 Xd, XZR, XZR, invert(cond) */
- unsigned int base = ext ? 0x9a9f07e0 : 0x1a9f07e0;
- tcg_out32(s, base | tcg_cond_to_aarch64[tcg_invert_cond(c)] << 12 | rd);
-}
-
static inline void tcg_out_goto(TCGContext *s, intptr_t target)
{
intptr_t offset = (target - (intptr_t)s->code_ptr) / 4;
@@ -1391,7 +1383,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
/* FALLTHRU */
case INDEX_op_setcond_i64:
tcg_out_cmp(s, ext, a1, a2, c2);
- tcg_out_cset(s, 0, a0, args[3]);
+ /* Use CSET alias of CSINC Wd, WZR, WZR, invert(cond). */
+ tcg_out_insn(s, 3506, CSINC, TCG_TYPE_I32, a0, TCG_REG_XZR,
+ TCG_REG_XZR, tcg_invert_cond(args[3]));
break;
case INDEX_op_movcond_i32:
--
1.8.5.3
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PULL 10/14] tcg-aarch64: Support deposit
2014-03-14 20:09 [Qemu-devel] [PULL 00/14] tcg/aarch64 improvements, part 2 Richard Henderson
` (8 preceding siblings ...)
2014-03-14 20:09 ` [Qemu-devel] [PULL 09/14] tcg-aarch64: Use tcg_out_insn for setcond Richard Henderson
@ 2014-03-14 20:09 ` Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 11/14] tcg-aarch64: Support add2, sub2 Richard Henderson
` (4 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2014-03-14 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, aliguori
Also tidy the implementation of ubfm, sbfm, extr in order to share code.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
Tested-by: Claudio Fontana <claudio.fontana@huawei.com>
---
tcg/aarch64/tcg-target.c | 66 ++++++++++++++++++++++++++++++++++--------------
tcg/aarch64/tcg-target.h | 4 +--
2 files changed, 49 insertions(+), 21 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index c38e3c0..26b30cb 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -269,6 +269,14 @@ typedef enum {
I3401_SUBI = 0x51000000,
I3401_SUBSI = 0x71000000,
+ /* Bitfield instructions. */
+ I3402_BFM = 0x33000000,
+ I3402_SBFM = 0x13000000,
+ I3402_UBFM = 0x53000000,
+
+ /* Extract instruction. */
+ I3403_EXTR = 0x13800000,
+
/* Logical immediate instructions. */
I3404_ANDI = 0x12000000,
I3404_ORRI = 0x32000000,
@@ -409,6 +417,13 @@ static void tcg_out_insn_3402(TCGContext *s, AArch64Insn insn, TCGType ext,
#define tcg_out_insn_3404 tcg_out_insn_3402
+static void tcg_out_insn_3403(TCGContext *s, AArch64Insn insn, TCGType ext,
+ TCGReg rd, TCGReg rn, TCGReg rm, int imms)
+{
+ tcg_out32(s, insn | ext << 31 | ext << 22 | rm << 16 | imms << 10
+ | rn << 5 | rd);
+}
+
/* This function is for both 3.5.2 (Add/Subtract shifted register), for
the rare occasion when we actually want to supply a shift amount. */
static inline void tcg_out_insn_3502S(TCGContext *s, AArch64Insn insn,
@@ -575,36 +590,35 @@ static inline void tcg_out_mul(TCGContext *s, TCGType ext,
tcg_out32(s, base | rm << 16 | rn << 5 | rd);
}
+static inline void tcg_out_bfm(TCGContext *s, TCGType ext, TCGReg rd,
+ TCGReg rn, unsigned int a, unsigned int b)
+{
+ tcg_out_insn(s, 3402, BFM, ext, rd, rn, ext, a, b);
+}
+
static inline void tcg_out_ubfm(TCGContext *s, TCGType ext, TCGReg rd,
TCGReg rn, unsigned int a, unsigned int b)
{
- /* Using UBFM 0x53000000 Wd, Wn, a, b */
- unsigned int base = ext ? 0xd3400000 : 0x53000000;
- tcg_out32(s, base | a << 16 | b << 10 | rn << 5 | rd);
+ tcg_out_insn(s, 3402, UBFM, ext, rd, rn, ext, a, b);
}
static inline void tcg_out_sbfm(TCGContext *s, TCGType ext, TCGReg rd,
TCGReg rn, unsigned int a, unsigned int b)
{
- /* Using SBFM 0x13000000 Wd, Wn, a, b */
- unsigned int base = ext ? 0x93400000 : 0x13000000;
- tcg_out32(s, base | a << 16 | b << 10 | rn << 5 | rd);
+ tcg_out_insn(s, 3402, SBFM, ext, rd, rn, ext, a, b);
}
static inline void tcg_out_extr(TCGContext *s, TCGType ext, TCGReg rd,
TCGReg rn, TCGReg rm, unsigned int a)
{
- /* Using EXTR 0x13800000 Wd, Wn, Wm, a */
- unsigned int base = ext ? 0x93c00000 : 0x13800000;
- tcg_out32(s, base | rm << 16 | a << 10 | rn << 5 | rd);
+ tcg_out_insn(s, 3403, EXTR, ext, rd, rn, rm, a);
}
static inline void tcg_out_shl(TCGContext *s, TCGType ext,
TCGReg rd, TCGReg rn, unsigned int m)
{
- int bits, max;
- bits = ext ? 64 : 32;
- max = bits - 1;
+ int bits = ext ? 64 : 32;
+ int max = bits - 1;
tcg_out_ubfm(s, ext, rd, rn, bits - (m & max), max - (m & max));
}
@@ -632,12 +646,20 @@ static inline void tcg_out_rotr(TCGContext *s, TCGType ext,
static inline void tcg_out_rotl(TCGContext *s, TCGType ext,
TCGReg rd, TCGReg rn, unsigned int m)
{
- int bits, max;
- bits = ext ? 64 : 32;
- max = bits - 1;
+ int bits = ext ? 64 : 32;
+ int max = bits - 1;
tcg_out_extr(s, ext, rd, rn, rn, bits - (m & max));
}
+static inline void tcg_out_dep(TCGContext *s, TCGType ext, TCGReg rd,
+ TCGReg rn, unsigned lsb, unsigned width)
+{
+ unsigned size = ext ? 64 : 32;
+ unsigned a = (size - lsb) & (size - 1);
+ unsigned b = width - 1;
+ tcg_out_bfm(s, ext, rd, rn, a, b);
+}
+
static void tcg_out_cmp(TCGContext *s, TCGType ext, TCGReg a,
tcg_target_long b, bool const_b)
{
@@ -786,8 +808,7 @@ static inline void tcg_out_rev16(TCGContext *s, TCGType ext,
static inline void tcg_out_sxt(TCGContext *s, TCGType ext, int s_bits,
TCGReg rd, TCGReg rn)
{
- /* using ALIASes SXTB 0x13001c00, SXTH 0x13003c00, SXTW 0x93407c00
- of SBFM Xd, Xn, #0, #7|15|31 */
+ /* Using ALIASes SXTB, SXTH, SXTW, of SBFM Xd, Xn, #0, #7|15|31 */
int bits = 8 * (1 << s_bits) - 1;
tcg_out_sbfm(s, ext, rd, rn, 0, bits);
}
@@ -795,8 +816,7 @@ static inline void tcg_out_sxt(TCGContext *s, TCGType ext, int s_bits,
static inline void tcg_out_uxt(TCGContext *s, int s_bits,
TCGReg rd, TCGReg rn)
{
- /* using ALIASes UXTB 0x53001c00, UXTH 0x53003c00
- of UBFM Wd, Wn, #0, #7|15 */
+ /* Using ALIASes UXTB, UXTH of UBFM Wd, Wn, #0, #7|15 */
int bits = 8 * (1 << s_bits) - 1;
tcg_out_ubfm(s, 0, rd, rn, 0, bits);
}
@@ -1469,6 +1489,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_movr(s, 0, a0, a1);
break;
+ case INDEX_op_deposit_i64:
+ case INDEX_op_deposit_i32:
+ tcg_out_dep(s, ext, a0, REG0(2), args[3], args[4]);
+ break;
+
case INDEX_op_mov_i64:
case INDEX_op_mov_i32:
case INDEX_op_movi_i64:
@@ -1590,6 +1615,9 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
{ INDEX_op_ext16u_i64, { "r", "r" } },
{ INDEX_op_ext32u_i64, { "r", "r" } },
+ { INDEX_op_deposit_i32, { "r", "0", "rZ" } },
+ { INDEX_op_deposit_i64, { "r", "0", "rZ" } },
+
{ -1 },
};
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 862600a..6bcd7ee 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -55,7 +55,7 @@ typedef enum {
#define TCG_TARGET_HAS_eqv_i32 1
#define TCG_TARGET_HAS_nand_i32 0
#define TCG_TARGET_HAS_nor_i32 0
-#define TCG_TARGET_HAS_deposit_i32 0
+#define TCG_TARGET_HAS_deposit_i32 1
#define TCG_TARGET_HAS_movcond_i32 1
#define TCG_TARGET_HAS_add2_i32 0
#define TCG_TARGET_HAS_sub2_i32 0
@@ -83,7 +83,7 @@ typedef enum {
#define TCG_TARGET_HAS_eqv_i64 1
#define TCG_TARGET_HAS_nand_i64 0
#define TCG_TARGET_HAS_nor_i64 0
-#define TCG_TARGET_HAS_deposit_i64 0
+#define TCG_TARGET_HAS_deposit_i64 1
#define TCG_TARGET_HAS_movcond_i64 1
#define TCG_TARGET_HAS_add2_i64 0
#define TCG_TARGET_HAS_sub2_i64 0
--
1.8.5.3
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PULL 11/14] tcg-aarch64: Support add2, sub2
2014-03-14 20:09 [Qemu-devel] [PULL 00/14] tcg/aarch64 improvements, part 2 Richard Henderson
` (9 preceding siblings ...)
2014-03-14 20:09 ` [Qemu-devel] [PULL 10/14] tcg-aarch64: Support deposit Richard Henderson
@ 2014-03-14 20:09 ` Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 12/14] tcg-aarch64: Support muluh, mulsh Richard Henderson
` (3 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2014-03-14 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, aliguori
Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
Tested-by: Claudio Fontana <claudio.fontana@huawei.com>
---
tcg/aarch64/tcg-target.c | 76 ++++++++++++++++++++++++++++++++++++++++++++++++
tcg/aarch64/tcg-target.h | 8 ++---
2 files changed, 80 insertions(+), 4 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 26b30cb..b9dc6bb 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -114,6 +114,7 @@ static inline void patch_reloc(uint8_t *code_ptr, int type,
#define TCG_CT_CONST_AIMM 0x200
#define TCG_CT_CONST_LIMM 0x400
#define TCG_CT_CONST_ZERO 0x800
+#define TCG_CT_CONST_MONE 0x1000
/* parse target specific constraints */
static int target_parse_constraint(TCGArgConstraint *ct,
@@ -147,6 +148,9 @@ static int target_parse_constraint(TCGArgConstraint *ct,
case 'L': /* Valid for logical immediate. */
ct->ct |= TCG_CT_CONST_LIMM;
break;
+ case 'M': /* minus one */
+ ct->ct |= TCG_CT_CONST_MONE;
+ break;
case 'Z': /* zero */
ct->ct |= TCG_CT_CONST_ZERO;
break;
@@ -204,6 +208,9 @@ static int tcg_target_const_match(tcg_target_long val,
if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
return 1;
}
+ if ((ct & TCG_CT_CONST_MONE) && val == -1) {
+ return 1;
+ }
return 0;
}
@@ -291,6 +298,10 @@ typedef enum {
/* Add/subtract shifted register instructions (with a shift). */
I3502S_ADD_LSL = I3502_ADD,
+ /* Add/subtract with carry instructions. */
+ I3503_ADC = 0x1a000000,
+ I3503_SBC = 0x5a000000,
+
/* Conditional select instructions. */
I3506_CSEL = 0x1a800000,
I3506_CSINC = 0x1a800400,
@@ -862,6 +873,47 @@ static void tcg_out_logicali(TCGContext *s, AArch64Insn insn, TCGType ext,
tcg_out_insn_3404(s, insn, ext, rd, rn, ext, r, c);
}
+static inline void tcg_out_addsub2(TCGContext *s, int ext, TCGReg rl,
+ TCGReg rh, TCGReg al, TCGReg ah,
+ tcg_target_long bl, tcg_target_long bh,
+ bool const_bl, bool const_bh, bool sub)
+{
+ TCGReg orig_rl = rl;
+ AArch64Insn insn;
+
+ if (rl == ah || (!const_bh && rl == bh)) {
+ rl = TCG_REG_TMP;
+ }
+
+ if (const_bl) {
+ insn = I3401_ADDSI;
+ if ((bl < 0) ^ sub) {
+ insn = I3401_SUBSI;
+ bl = -bl;
+ }
+ tcg_out_insn_3401(s, insn, ext, rl, al, bl);
+ } else {
+ tcg_out_insn_3502(s, sub ? I3502_SUBS : I3502_ADDS, ext, rl, al, bl);
+ }
+
+ insn = I3503_ADC;
+ if (const_bh) {
+ /* Note that the only two constants we support are 0 and -1, and
+ that SBC = rn + ~rm + c, so adc -1 is sbc 0, and vice-versa. */
+ if ((bh != 0) ^ sub) {
+ insn = I3503_SBC;
+ }
+ bh = TCG_REG_XZR;
+ } else if (sub) {
+ insn = I3503_SBC;
+ }
+ tcg_out_insn_3503(s, insn, ext, rh, ah, bh);
+
+ if (rl != orig_rl) {
+ tcg_out_movr(s, ext, orig_rl, rl);
+ }
+}
+
#ifdef CONFIG_SOFTMMU
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
* int mmu_idx, uintptr_t ra)
@@ -1494,6 +1546,25 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_dep(s, ext, a0, REG0(2), args[3], args[4]);
break;
+ case INDEX_op_add2_i32:
+ tcg_out_addsub2(s, TCG_TYPE_I32, a0, a1, REG0(2), REG0(3),
+ (int32_t)args[4], args[5], const_args[4],
+ const_args[5], false);
+ break;
+ case INDEX_op_add2_i64:
+ tcg_out_addsub2(s, TCG_TYPE_I64, a0, a1, REG0(2), REG0(3), args[4],
+ args[5], const_args[4], const_args[5], false);
+ break;
+ case INDEX_op_sub2_i32:
+ tcg_out_addsub2(s, TCG_TYPE_I32, a0, a1, REG0(2), REG0(3),
+ (int32_t)args[4], args[5], const_args[4],
+ const_args[5], true);
+ break;
+ case INDEX_op_sub2_i64:
+ tcg_out_addsub2(s, TCG_TYPE_I64, a0, a1, REG0(2), REG0(3), args[4],
+ args[5], const_args[4], const_args[5], true);
+ break;
+
case INDEX_op_mov_i64:
case INDEX_op_mov_i32:
case INDEX_op_movi_i64:
@@ -1618,6 +1689,11 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
{ INDEX_op_deposit_i32, { "r", "0", "rZ" } },
{ INDEX_op_deposit_i64, { "r", "0", "rZ" } },
+ { INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rwA", "rwMZ" } },
+ { INDEX_op_add2_i64, { "r", "r", "rZ", "rZ", "rA", "rMZ" } },
+ { INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rwA", "rwMZ" } },
+ { INDEX_op_sub2_i64, { "r", "r", "rZ", "rZ", "rA", "rMZ" } },
+
{ -1 },
};
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 6bcd7ee..f174ebd 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -57,8 +57,8 @@ typedef enum {
#define TCG_TARGET_HAS_nor_i32 0
#define TCG_TARGET_HAS_deposit_i32 1
#define TCG_TARGET_HAS_movcond_i32 1
-#define TCG_TARGET_HAS_add2_i32 0
-#define TCG_TARGET_HAS_sub2_i32 0
+#define TCG_TARGET_HAS_add2_i32 1
+#define TCG_TARGET_HAS_sub2_i32 1
#define TCG_TARGET_HAS_mulu2_i32 0
#define TCG_TARGET_HAS_muls2_i32 0
#define TCG_TARGET_HAS_muluh_i32 0
@@ -85,8 +85,8 @@ typedef enum {
#define TCG_TARGET_HAS_nor_i64 0
#define TCG_TARGET_HAS_deposit_i64 1
#define TCG_TARGET_HAS_movcond_i64 1
-#define TCG_TARGET_HAS_add2_i64 0
-#define TCG_TARGET_HAS_sub2_i64 0
+#define TCG_TARGET_HAS_add2_i64 1
+#define TCG_TARGET_HAS_sub2_i64 1
#define TCG_TARGET_HAS_mulu2_i64 0
#define TCG_TARGET_HAS_muls2_i64 0
#define TCG_TARGET_HAS_muluh_i64 0
--
1.8.5.3
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PULL 12/14] tcg-aarch64: Support muluh, mulsh
2014-03-14 20:09 [Qemu-devel] [PULL 00/14] tcg/aarch64 improvements, part 2 Richard Henderson
` (10 preceding siblings ...)
2014-03-14 20:09 ` [Qemu-devel] [PULL 11/14] tcg-aarch64: Support add2, sub2 Richard Henderson
@ 2014-03-14 20:09 ` Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 13/14] tcg-aarch64: Support div, rem Richard Henderson
` (2 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2014-03-14 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, aliguori
Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
Tested-by: Claudio Fontana <claudio.fontana@huawei.com>
---
tcg/aarch64/tcg-target.c | 12 ++++++++++++
tcg/aarch64/tcg-target.h | 4 ++--
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index b9dc6bb..9c50820 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -311,6 +311,8 @@ typedef enum {
I3508_LSRV = 0x1ac02400,
I3508_ASRV = 0x1ac02800,
I3508_RORV = 0x1ac02c00,
+ I3508_SMULH = 0x9b407c00,
+ I3508_UMULH = 0x9bc07c00,
/* Logical shifted register instructions (without a shift). */
I3510_AND = 0x0a000000,
@@ -1565,6 +1567,13 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
args[5], const_args[4], const_args[5], true);
break;
+ case INDEX_op_muluh_i64:
+ tcg_out_insn(s, 3508, UMULH, TCG_TYPE_I64, a0, a1, a2);
+ break;
+ case INDEX_op_mulsh_i64:
+ tcg_out_insn(s, 3508, SMULH, TCG_TYPE_I64, a0, a1, a2);
+ break;
+
case INDEX_op_mov_i64:
case INDEX_op_mov_i32:
case INDEX_op_movi_i64:
@@ -1694,6 +1703,9 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
{ INDEX_op_sub2_i32, { "r", "r", "rZ", "rZ", "rwA", "rwMZ" } },
{ INDEX_op_sub2_i64, { "r", "r", "rZ", "rZ", "rA", "rMZ" } },
+ { INDEX_op_muluh_i64, { "r", "r", "r" } },
+ { INDEX_op_mulsh_i64, { "r", "r", "r" } },
+
{ -1 },
};
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index f174ebd..c819095 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -89,8 +89,8 @@ typedef enum {
#define TCG_TARGET_HAS_sub2_i64 1
#define TCG_TARGET_HAS_mulu2_i64 0
#define TCG_TARGET_HAS_muls2_i64 0
-#define TCG_TARGET_HAS_muluh_i64 0
-#define TCG_TARGET_HAS_mulsh_i64 0
+#define TCG_TARGET_HAS_muluh_i64 1
+#define TCG_TARGET_HAS_mulsh_i64 1
enum {
TCG_AREG0 = TCG_REG_X19,
--
1.8.5.3
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PULL 13/14] tcg-aarch64: Support div, rem
2014-03-14 20:09 [Qemu-devel] [PULL 00/14] tcg/aarch64 improvements, part 2 Richard Henderson
` (11 preceding siblings ...)
2014-03-14 20:09 ` [Qemu-devel] [PULL 12/14] tcg-aarch64: Support muluh, mulsh Richard Henderson
@ 2014-03-14 20:09 ` Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 14/14] tcg-aarch64: Introduce tcg_out_insn_3405 Richard Henderson
2014-03-15 18:24 ` [Qemu-devel] [PULL 00/14] tcg/aarch64 improvements, part 2 Peter Maydell
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2014-03-14 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, aliguori
Clean up multiply at the same time.
For remainder, generic code will produce mul+sub,
whereas we can implement with msub.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
Tested-by: Claudio Fontana <claudio.fontana@huawei.com>
---
tcg/aarch64/tcg-target.c | 50 +++++++++++++++++++++++++++++++++++++++---------
tcg/aarch64/tcg-target.h | 8 ++++----
2 files changed, 45 insertions(+), 13 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 9c50820..23bbe95 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -313,6 +313,12 @@ typedef enum {
I3508_RORV = 0x1ac02c00,
I3508_SMULH = 0x9b407c00,
I3508_UMULH = 0x9bc07c00,
+ I3508_UDIV = 0x1ac00800,
+ I3508_SDIV = 0x1ac00c00,
+
+ /* Data-processing (3 source) instructions. */
+ I3509_MADD = 0x1b000000,
+ I3509_MSUB = 0x1b008000,
/* Logical shifted register instructions (without a shift). */
I3510_AND = 0x0a000000,
@@ -467,6 +473,12 @@ static void tcg_out_insn_3506(TCGContext *s, AArch64Insn insn, TCGType ext,
| tcg_cond_to_aarch64[c] << 12);
}
+static void tcg_out_insn_3509(TCGContext *s, AArch64Insn insn, TCGType ext,
+ TCGReg rd, TCGReg rn, TCGReg rm, TCGReg ra)
+{
+ tcg_out32(s, insn | ext << 31 | rm << 16 | ra << 10 | rn << 5 | rd);
+}
+
static inline void tcg_out_ldst_9(TCGContext *s,
enum aarch64_ldst_op_data op_data,
@@ -595,14 +607,6 @@ static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
arg, arg1, arg2);
}
-static inline void tcg_out_mul(TCGContext *s, TCGType ext,
- TCGReg rd, TCGReg rn, TCGReg rm)
-{
- /* Using MADD 0x1b000000 with Ra = wzr alias MUL 0x1b007c00 */
- unsigned int base = ext ? 0x9b007c00 : 0x1b007c00;
- tcg_out32(s, base | rm << 16 | rn << 5 | rd);
-}
-
static inline void tcg_out_bfm(TCGContext *s, TCGType ext, TCGReg rd,
TCGReg rn, unsigned int a, unsigned int b)
{
@@ -1395,7 +1399,27 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_mul_i64:
case INDEX_op_mul_i32:
- tcg_out_mul(s, ext, a0, a1, a2);
+ tcg_out_insn(s, 3509, MADD, ext, a0, a1, a2, TCG_REG_XZR);
+ break;
+
+ case INDEX_op_div_i64:
+ case INDEX_op_div_i32:
+ tcg_out_insn(s, 3508, SDIV, ext, a0, a1, a2);
+ break;
+ case INDEX_op_divu_i64:
+ case INDEX_op_divu_i32:
+ tcg_out_insn(s, 3508, UDIV, ext, a0, a1, a2);
+ break;
+
+ case INDEX_op_rem_i64:
+ case INDEX_op_rem_i32:
+ tcg_out_insn(s, 3508, SDIV, ext, TCG_REG_TMP, a1, a2);
+ tcg_out_insn(s, 3509, MSUB, ext, a0, TCG_REG_TMP, a2, a1);
+ break;
+ case INDEX_op_remu_i64:
+ case INDEX_op_remu_i32:
+ tcg_out_insn(s, 3508, UDIV, ext, TCG_REG_TMP, a1, a2);
+ tcg_out_insn(s, 3509, MSUB, ext, a0, TCG_REG_TMP, a2, a1);
break;
case INDEX_op_shl_i64:
@@ -1626,6 +1650,14 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
{ INDEX_op_sub_i64, { "r", "r", "rA" } },
{ INDEX_op_mul_i32, { "r", "r", "r" } },
{ INDEX_op_mul_i64, { "r", "r", "r" } },
+ { INDEX_op_div_i32, { "r", "r", "r" } },
+ { INDEX_op_div_i64, { "r", "r", "r" } },
+ { INDEX_op_divu_i32, { "r", "r", "r" } },
+ { INDEX_op_divu_i64, { "r", "r", "r" } },
+ { INDEX_op_rem_i32, { "r", "r", "r" } },
+ { INDEX_op_rem_i64, { "r", "r", "r" } },
+ { INDEX_op_remu_i32, { "r", "r", "r" } },
+ { INDEX_op_remu_i64, { "r", "r", "r" } },
{ INDEX_op_and_i32, { "r", "r", "rwL" } },
{ INDEX_op_and_i64, { "r", "r", "rL" } },
{ INDEX_op_or_i32, { "r", "r", "rwL" } },
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index c819095..988983e 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -39,8 +39,8 @@ typedef enum {
#define TCG_TARGET_CALL_STACK_OFFSET 0
/* optional instructions */
-#define TCG_TARGET_HAS_div_i32 0
-#define TCG_TARGET_HAS_rem_i32 0
+#define TCG_TARGET_HAS_div_i32 1
+#define TCG_TARGET_HAS_rem_i32 1
#define TCG_TARGET_HAS_ext8s_i32 1
#define TCG_TARGET_HAS_ext16s_i32 1
#define TCG_TARGET_HAS_ext8u_i32 1
@@ -64,8 +64,8 @@ typedef enum {
#define TCG_TARGET_HAS_muluh_i32 0
#define TCG_TARGET_HAS_mulsh_i32 0
-#define TCG_TARGET_HAS_div_i64 0
-#define TCG_TARGET_HAS_rem_i64 0
+#define TCG_TARGET_HAS_div_i64 1
+#define TCG_TARGET_HAS_rem_i64 1
#define TCG_TARGET_HAS_ext8s_i64 1
#define TCG_TARGET_HAS_ext16s_i64 1
#define TCG_TARGET_HAS_ext32s_i64 1
--
1.8.5.3
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PULL 14/14] tcg-aarch64: Introduce tcg_out_insn_3405
2014-03-14 20:09 [Qemu-devel] [PULL 00/14] tcg/aarch64 improvements, part 2 Richard Henderson
` (12 preceding siblings ...)
2014-03-14 20:09 ` [Qemu-devel] [PULL 13/14] tcg-aarch64: Support div, rem Richard Henderson
@ 2014-03-14 20:09 ` Richard Henderson
2014-03-15 18:24 ` [Qemu-devel] [PULL 00/14] tcg/aarch64 improvements, part 2 Peter Maydell
14 siblings, 0 replies; 16+ messages in thread
From: Richard Henderson @ 2014-03-14 20:09 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, aliguori
Cleaning up the implementation of tcg_out_movi at the same time.
Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
Tested-by: Claudio Fontana <claudio.fontana@huawei.com>
---
tcg/aarch64/tcg-target.c | 48 +++++++++++++++++++++++++++---------------------
1 file changed, 27 insertions(+), 21 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 23bbe95..661a5af 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -289,6 +289,11 @@ typedef enum {
I3404_ORRI = 0x32000000,
I3404_EORI = 0x52000000,
+ /* Move wide immediate instructions. */
+ I3405_MOVN = 0x12800000,
+ I3405_MOVZ = 0x52800000,
+ I3405_MOVK = 0x72800000,
+
/* Add/subtract shifted register instructions (without a shift). */
I3502_ADD = 0x0b000000,
I3502_ADDS = 0x2b000000,
@@ -443,6 +448,15 @@ static void tcg_out_insn_3403(TCGContext *s, AArch64Insn insn, TCGType ext,
| rn << 5 | rd);
}
+/* This function is used for the Move (wide immediate) instruction group.
+ Note that SHIFT is a full shift count, not the 2 bit HW field. */
+static void tcg_out_insn_3405(TCGContext *s, AArch64Insn insn, TCGType ext,
+ TCGReg rd, uint16_t half, unsigned shift)
+{
+ assert((shift & ~0x30) == 0);
+ tcg_out32(s, insn | ext << 31 | shift << (21 - 4) | half << 5 | rd);
+}
+
/* This function is for both 3.5.2 (Add/Subtract shifted register), for
the rare occasion when we actually want to supply a shift amount. */
static inline void tcg_out_insn_3502S(TCGContext *s, AArch64Insn insn,
@@ -513,38 +527,30 @@ static void tcg_out_movr_sp(TCGContext *s, TCGType ext, TCGReg rd, TCGReg rn)
tcg_out_insn(s, 3401, ADDI, ext, rd, rn, 0);
}
-static inline void tcg_out_movi_aux(TCGContext *s,
- TCGReg rd, uint64_t value)
+static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
+ tcg_target_long value)
{
- uint32_t half, base, shift, movk = 0;
- /* construct halfwords of the immediate with MOVZ/MOVK with LSL */
- /* using MOVZ 0x52800000 | extended reg.. */
- base = (value > 0xffffffff) ? 0xd2800000 : 0x52800000;
+ AArch64Insn insn;
+
+ if (type == TCG_TYPE_I32) {
+ value = (uint32_t)value;
+ }
+
/* count trailing zeros in 16 bit steps, mapping 64 to 0. Emit the
first MOVZ with the half-word immediate skipping the zeros, with a shift
- (LSL) equal to this number. Then morph all next instructions into MOVKs.
+ (LSL) equal to this number. Then all next instructions use MOVKs.
Zero the processed half-word in the value, continue until empty.
We build the final result 16bits at a time with up to 4 instructions,
but do not emit instructions for 16bit zero holes. */
+ insn = I3405_MOVZ;
do {
- shift = ctz64(value) & (63 & -16);
- half = (value >> shift) & 0xffff;
- tcg_out32(s, base | movk | shift << 17 | half << 5 | rd);
- movk = 0x20000000; /* morph next MOVZs into MOVKs */
+ unsigned shift = ctz64(value) & (63 & -16);
+ tcg_out_insn_3405(s, insn, shift >= 32, rd, value >> shift, shift);
value &= ~(0xffffUL << shift);
+ insn = I3405_MOVK;
} while (value);
}
-static inline void tcg_out_movi(TCGContext *s, TCGType type,
- TCGReg rd, tcg_target_long value)
-{
- if (type == TCG_TYPE_I64) {
- tcg_out_movi_aux(s, rd, value);
- } else {
- tcg_out_movi_aux(s, rd, value & 0xffffffff);
- }
-}
-
static inline void tcg_out_ldst_r(TCGContext *s,
enum aarch64_ldst_op_data op_data,
enum aarch64_ldst_op_type op_type,
--
1.8.5.3
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [Qemu-devel] [PULL 00/14] tcg/aarch64 improvements, part 2
2014-03-14 20:09 [Qemu-devel] [PULL 00/14] tcg/aarch64 improvements, part 2 Richard Henderson
` (13 preceding siblings ...)
2014-03-14 20:09 ` [Qemu-devel] [PULL 14/14] tcg-aarch64: Introduce tcg_out_insn_3405 Richard Henderson
@ 2014-03-15 18:24 ` Peter Maydell
14 siblings, 0 replies; 16+ messages in thread
From: Peter Maydell @ 2014-03-15 18:24 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Developers, Anthony Liguori
On 14 March 2014 20:09, Richard Henderson <rth@twiddle.net> wrote:
> Recently reviewed.
>
> It'd be nice if this makes -rc1, since it significantly improves code
> generation for the host. But it's no big deal if it's too late.
>
>
> r~
>
>
> The following changes since commit b19fc63cadb2815d5bcb1ec25b22849e455cbb31:
>
> Merge remote-tracking branch 'remotes/afaerber/tags/qom-devices-for-2.0' into staging (2014-03-13 21:50:40 +0000)
>
> are available in the git repository at:
>
>
> git://github.com/rth7680/qemu.git tcg-aarch-6-2
>
> for you to fetch changes up to 582ab779c5cf9c941909faa65e092b6b492e2da6:
>
> tcg-aarch64: Introduce tcg_out_insn_3405 (2014-03-14 11:00:15 -0700)
Applied, thanks.
-- PMM
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2014-03-15 18:24 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-03-14 20:09 [Qemu-devel] [PULL 00/14] tcg/aarch64 improvements, part 2 Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 01/14] tcg-aarch64: Introduce tcg_out_insn Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 02/14] tcg-aarch64: Convert shift insns to tcg_out_insn Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 03/14] tcg-aarch64: Introduce tcg_out_insn_3401 Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 04/14] tcg-aarch64: Implement mov with tcg_out_insn Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 05/14] tcg-aarch64: Handle constant operands to add, sub, and compare Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 06/14] tcg-aarch64: Handle constant operands to and, or, xor Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 07/14] tcg-aarch64: Support andc, orc, eqv, not, neg Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 08/14] tcg-aarch64: Support movcond Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 09/14] tcg-aarch64: Use tcg_out_insn for setcond Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 10/14] tcg-aarch64: Support deposit Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 11/14] tcg-aarch64: Support add2, sub2 Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 12/14] tcg-aarch64: Support muluh, mulsh Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 13/14] tcg-aarch64: Support div, rem Richard Henderson
2014-03-14 20:09 ` [Qemu-devel] [PULL 14/14] tcg-aarch64: Introduce tcg_out_insn_3405 Richard Henderson
2014-03-15 18:24 ` [Qemu-devel] [PULL 00/14] tcg/aarch64 improvements, part 2 Peter Maydell
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