From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53883) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WOoEU-0004fK-1a for qemu-devel@nongnu.org; Sat, 15 Mar 2014 09:02:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WOoEO-0003bR-7y for qemu-devel@nongnu.org; Sat, 15 Mar 2014 09:02:33 -0400 Received: from mail-ee0-x236.google.com ([2a00:1450:4013:c00::236]:60204) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WOoEO-0003bK-13 for qemu-devel@nongnu.org; Sat, 15 Mar 2014 09:02:28 -0400 Received: by mail-ee0-f54.google.com with SMTP id d49so2389108eek.27 for ; Sat, 15 Mar 2014 06:02:27 -0700 (PDT) From: Beniamino Galvani Date: Sat, 15 Mar 2014 14:01:33 +0100 Message-Id: <1394888493-20487-8-git-send-email-b.galvani@gmail.com> In-Reply-To: <1394888493-20487-1-git-send-email-b.galvani@gmail.com> References: <1394888493-20487-1-git-send-email-b.galvani@gmail.com> Subject: [Qemu-devel] [PATCH v3 7/7] allwinner-emac: update irq status after writes to interrupt registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Beniamino Galvani , Peter Maydell , Peter Crosthwaite , Li Guang The irq line status must be updated after writes to the INT_CTL and INT_STA registers. Signed-off-by: Beniamino Galvani Reviewed-by: Peter Crosthwaite --- hw/net/allwinner_emac.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/net/allwinner_emac.c b/hw/net/allwinner_emac.c index 91931ac..d780ba0 100644 --- a/hw/net/allwinner_emac.c +++ b/hw/net/allwinner_emac.c @@ -391,9 +391,11 @@ static void aw_emac_write(void *opaque, hwaddr offset, uint64_t value, break; case EMAC_INT_CTL_REG: s->int_ctl = value; + aw_emac_update_irq(s); break; case EMAC_INT_STA_REG: s->int_sta &= ~value; + aw_emac_update_irq(s); break; case EMAC_MAC_MADR_REG: s->phy_target = value; -- 1.7.10.4