From: Li Guang <lig.fnst@cn.fujitsu.com>
To: Beniamino Galvani <b.galvani@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>,
Peter Crosthwaite <peter.crosthwaite@xilinx.com>,
qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH v3 1/7] allwinner-a10-pic: set vector address when an interrupt is pending
Date: Mon, 17 Mar 2014 09:16:43 +0800 [thread overview]
Message-ID: <1395019003.2364.1.camel@localhost> (raw)
In-Reply-To: <1394888493-20487-2-git-send-email-b.galvani@gmail.com>
在 2014-03-15六的 14:01 +0100,Beniamino Galvani写道:
> This patch implements proper updating of the vector register which
> should hold, according to the A10 user manual, the vector address for
> the interrupt currently active on the CPU IRQ input.
>
> Interrupt priority is not implemented at the moment and thus the first
> pending interrupt is returned.
>
> Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Li Guang <lig.fnst@cn.fujitsu.com>
> ---
> hw/intc/allwinner-a10-pic.c | 14 ++++++++++----
> 1 file changed, 10 insertions(+), 4 deletions(-)
>
> diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c
> index 407d563..00f3c11 100644
> --- a/hw/intc/allwinner-a10-pic.c
> +++ b/hw/intc/allwinner-a10-pic.c
> @@ -23,11 +23,20 @@
> static void aw_a10_pic_update(AwA10PICState *s)
> {
> uint8_t i;
> - int irq = 0, fiq = 0;
> + int irq = 0, fiq = 0, pending;
> +
> + s->vector = 0;
>
> for (i = 0; i < AW_A10_PIC_REG_NUM; i++) {
> irq |= s->irq_pending[i] & ~s->mask[i];
> fiq |= s->select[i] & s->irq_pending[i] & ~s->mask[i];
> +
> + if (!s->vector) {
> + pending = ffs(s->irq_pending[i] & ~s->mask[i]);
> + if (pending) {
> + s->vector = (i * 32 + pending - 1) * 4;
> + }
> + }
> }
>
> qemu_set_irq(s->parent_irq, !!irq);
> @@ -84,9 +93,6 @@ static void aw_a10_pic_write(void *opaque, hwaddr offset, uint64_t value,
> uint8_t index = (offset & 0xc) / 4;
>
> switch (offset) {
> - case AW_A10_PIC_VECTOR:
> - s->vector = value & ~0x3;
> - break;
> case AW_A10_PIC_BASE_ADDR:
> s->base_addr = value & ~0x3;
> case AW_A10_PIC_PROTECT:
next prev parent reply other threads:[~2014-03-17 1:22 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-03-15 13:01 [Qemu-devel] [PATCH v3 0/7] Allwinner A10 fixes Beniamino Galvani
2014-03-15 13:01 ` [Qemu-devel] [PATCH v3 1/7] allwinner-a10-pic: set vector address when an interrupt is pending Beniamino Galvani
2014-03-17 1:16 ` Li Guang [this message]
2014-03-15 13:01 ` [Qemu-devel] [PATCH v3 2/7] allwinner-a10-pic: fix behaviour of pending register Beniamino Galvani
2014-03-17 1:00 ` Peter Crosthwaite
2014-03-17 1:17 ` Li Guang
2014-03-15 13:01 ` [Qemu-devel] [PATCH v3 3/7] allwinner-a10-pit: avoid generation of spurious interrupts Beniamino Galvani
2014-03-17 1:02 ` Peter Crosthwaite
2014-03-17 1:17 ` Li Guang
2014-03-15 13:01 ` [Qemu-devel] [PATCH v3 4/7] allwinner-a10-pit: use level triggered interrupts Beniamino Galvani
2014-03-17 1:10 ` Peter Crosthwaite
2014-03-15 13:01 ` [Qemu-devel] [PATCH v3 5/7] allwinner-a10-pit: implement prescaler and source selection Beniamino Galvani
2014-03-17 1:18 ` Li Guang
2014-03-17 1:27 ` Peter Crosthwaite
2014-03-17 20:45 ` Beniamino Galvani
2014-03-15 13:01 ` [Qemu-devel] [PATCH v3 6/7] allwinner-emac: set autonegotiation complete bit on link up Beniamino Galvani
2014-03-17 1:29 ` Peter Crosthwaite
2014-03-15 13:01 ` [Qemu-devel] [PATCH v3 7/7] allwinner-emac: update irq status after writes to interrupt registers Beniamino Galvani
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