From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39559) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPMGM-0004zS-8Y for qemu-devel@nongnu.org; Sun, 16 Mar 2014 21:22:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WPMGE-0001VW-TH for qemu-devel@nongnu.org; Sun, 16 Mar 2014 21:22:46 -0400 Received: from [222.73.24.84] (port=40502 helo=song.cn.fujitsu.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPMGE-0001TD-EF for qemu-devel@nongnu.org; Sun, 16 Mar 2014 21:22:38 -0400 Message-ID: <1395019003.2364.1.camel@localhost> From: Li Guang Date: Mon, 17 Mar 2014 09:16:43 +0800 In-Reply-To: <1394888493-20487-2-git-send-email-b.galvani@gmail.com> References: <1394888493-20487-1-git-send-email-b.galvani@gmail.com> <1394888493-20487-2-git-send-email-b.galvani@gmail.com> Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="UTF-8" Subject: Re: [Qemu-devel] [PATCH v3 1/7] allwinner-a10-pic: set vector address when an interrupt is pending List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Beniamino Galvani Cc: Peter Maydell , Peter Crosthwaite , qemu-devel@nongnu.org =E5=9C=A8 2014-03-15=E5=85=AD=E7=9A=84 14:01 +0100=EF=BC=8CBeniamino Galvan= i=E5=86=99=E9=81=93=EF=BC=9A > This patch implements proper updating of the vector register which > should hold, according to the A10 user manual, the vector address for > the interrupt currently active on the CPU IRQ input. >=20 > Interrupt priority is not implemented at the moment and thus the first > pending interrupt is returned. >=20 > Signed-off-by: Beniamino Galvani > Reviewed-by: Peter Crosthwaite Reviewed-by: Li Guang > --- > hw/intc/allwinner-a10-pic.c | 14 ++++++++++---- > 1 file changed, 10 insertions(+), 4 deletions(-) >=20 > diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c > index 407d563..00f3c11 100644 > --- a/hw/intc/allwinner-a10-pic.c > +++ b/hw/intc/allwinner-a10-pic.c > @@ -23,11 +23,20 @@ > static void aw_a10_pic_update(AwA10PICState *s) > { > uint8_t i; > - int irq =3D 0, fiq =3D 0; > + int irq =3D 0, fiq =3D 0, pending; > + > + s->vector =3D 0; > =20 > for (i =3D 0; i < AW_A10_PIC_REG_NUM; i++) { > irq |=3D s->irq_pending[i] & ~s->mask[i]; > fiq |=3D s->select[i] & s->irq_pending[i] & ~s->mask[i]; > + > + if (!s->vector) { > + pending =3D ffs(s->irq_pending[i] & ~s->mask[i]); > + if (pending) { > + s->vector =3D (i * 32 + pending - 1) * 4; > + } > + } > } > =20 > qemu_set_irq(s->parent_irq, !!irq); > @@ -84,9 +93,6 @@ static void aw_a10_pic_write(void *opaque, hwaddr offse= t, uint64_t value, > uint8_t index =3D (offset & 0xc) / 4; > =20 > switch (offset) { > - case AW_A10_PIC_VECTOR: > - s->vector =3D value & ~0x3; > - break; > case AW_A10_PIC_BASE_ADDR: > s->base_addr =3D value & ~0x3; > case AW_A10_PIC_PROTECT: