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From: Li Guang <lig.fnst@cn.fujitsu.com>
Date: Mon, 17 Mar 2014 09:17:01 +0800
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Subject: Re: [Qemu-devel] [PATCH v3 2/7] allwinner-a10-pic: fix behaviour of
 pending register
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To: Beniamino Galvani <b.galvani@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>, Peter Crosthwaite <peter.crosthwaite@xilinx.com>, qemu-devel@nongnu.org

=E5=9C=A8 2014-03-15=E5=85=AD=E7=9A=84 14:01 +0100=EF=BC=8CBeniamino Galvan=
i=E5=86=99=E9=81=93=EF=BC=9A
> The pending register is read-only and the value returned upon a read
> reflects the state of irq input pins (interrupts are level triggered).
> This patch implements such behaviour.
>=20
> Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>

Reviewed-by: Li Guang <lig.fnst@cn.fujitsu.com>

> ---
>  hw/intc/allwinner-a10-pic.c |    8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
>=20
> diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c
> index 00f3c11..0924d98 100644
> --- a/hw/intc/allwinner-a10-pic.c
> +++ b/hw/intc/allwinner-a10-pic.c
> @@ -49,6 +49,8 @@ static void aw_a10_pic_set_irq(void *opaque, int irq, i=
nt level)
> =20
>      if (level) {
>          set_bit(irq % 32, (void *)&s->irq_pending[irq / 32]);
> +    } else {
> +        clear_bit(irq % 32, (void *)&s->irq_pending[irq / 32]);
>      }
>      aw_a10_pic_update(s);
>  }
> @@ -102,7 +104,11 @@ static void aw_a10_pic_write(void *opaque, hwaddr of=
fset, uint64_t value,
>          s->nmi =3D value;
>          break;
>      case AW_A10_PIC_IRQ_PENDING ... AW_A10_PIC_IRQ_PENDING + 8:
> -        s->irq_pending[index] &=3D ~value;
> +        /*
> +         * The register is read-only; nevertheless, Linux (including
> +         * the version originally shipped by Allwinner) pretends to
> +         * write to the register. Just ignore it.
> +         */
>          break;
>      case AW_A10_PIC_FIQ_PENDING ... AW_A10_PIC_FIQ_PENDING + 8:
>          s->fiq_pending[index] &=3D ~value;