From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39561) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPMGM-0004zT-C4 for qemu-devel@nongnu.org; Sun, 16 Mar 2014 21:22:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WPMGE-0001VQ-IJ for qemu-devel@nongnu.org; Sun, 16 Mar 2014 21:22:46 -0400 Received: from [222.73.24.84] (port=41801 helo=song.cn.fujitsu.com) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPMGE-0001T3-3C for qemu-devel@nongnu.org; Sun, 16 Mar 2014 21:22:38 -0400 Message-ID: <1395019048.2364.3.camel@localhost> From: Li Guang Date: Mon, 17 Mar 2014 09:17:28 +0800 In-Reply-To: <1394888493-20487-4-git-send-email-b.galvani@gmail.com> References: <1394888493-20487-1-git-send-email-b.galvani@gmail.com> <1394888493-20487-4-git-send-email-b.galvani@gmail.com> Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="UTF-8" Subject: Re: [Qemu-devel] [PATCH v3 3/7] allwinner-a10-pit: avoid generation of spurious interrupts List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Beniamino Galvani Cc: Peter Maydell , Peter Crosthwaite , qemu-devel@nongnu.org =E5=9C=A8 2014-03-15=E5=85=AD=E7=9A=84 14:01 +0100=EF=BC=8CBeniamino Galvan= i=E5=86=99=E9=81=93=EF=BC=9A > The model was generating interrupts for all enabled timers after the > expiration of one of them. Avoid this by passing explicitly the timer > index to the callback function. >=20 > Signed-off-by: Beniamino Galvani Reviewed-by: Li Guang > --- > hw/timer/allwinner-a10-pit.c | 25 ++++++++++++++----------- > include/hw/timer/allwinner-a10-pit.h | 8 ++++++++ > 2 files changed, 22 insertions(+), 11 deletions(-) >=20 > diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c > index b27fce8..696b7d9 100644 > --- a/hw/timer/allwinner-a10-pit.c > +++ b/hw/timer/allwinner-a10-pit.c > @@ -193,18 +193,17 @@ static void a10_pit_reset(DeviceState *dev) > =20 > static void a10_pit_timer_cb(void *opaque) > { > - AwA10PITState *s =3D AW_A10_PIT(opaque); > - uint8_t i; > + AwA10TimerContext *tc =3D opaque; > + AwA10PITState *s =3D tc->container; > + uint8_t i =3D tc->index; > =20 > - for (i =3D 0; i < AW_A10_PIT_TIMER_NR; i++) { > - if (s->control[i] & AW_A10_PIT_TIMER_EN) { > - s->irq_status |=3D 1 << i; > - if (s->control[i] & AW_A10_PIT_TIMER_MODE) { > - ptimer_stop(s->timer[i]); > - s->control[i] &=3D ~AW_A10_PIT_TIMER_EN; > - } > - qemu_irq_pulse(s->irq[i]); > + if (s->control[i] & AW_A10_PIT_TIMER_EN) { > + s->irq_status |=3D 1 << i; > + if (s->control[i] & AW_A10_PIT_TIMER_MODE) { > + ptimer_stop(s->timer[i]); > + s->control[i] &=3D ~AW_A10_PIT_TIMER_EN; > } > + qemu_irq_pulse(s->irq[i]); > } > } > =20 > @@ -223,7 +222,11 @@ static void a10_pit_init(Object *obj) > sysbus_init_mmio(sbd, &s->iomem); > =20 > for (i =3D 0; i < AW_A10_PIT_TIMER_NR; i++) { > - bh[i] =3D qemu_bh_new(a10_pit_timer_cb, s); > + AwA10TimerContext *tc =3D &s->timer_context[i]; > + > + tc->container =3D s; > + tc->index =3D i; > + bh[i] =3D qemu_bh_new(a10_pit_timer_cb, tc); > s->timer[i] =3D ptimer_init(bh[i]); > ptimer_set_freq(s->timer[i], 240000); > } > diff --git a/include/hw/timer/allwinner-a10-pit.h b/include/hw/timer/allw= inner-a10-pit.h > index 15efab8..a48d3c7 100644 > --- a/include/hw/timer/allwinner-a10-pit.h > +++ b/include/hw/timer/allwinner-a10-pit.h > @@ -35,12 +35,20 @@ > =20 > #define AW_A10_PIT_DEFAULT_CLOCK 0x4 > =20 > +typedef struct AwA10PITState AwA10PITState; > + > +typedef struct AwA10TimerContext { > + AwA10PITState *container; > + int index; > +} AwA10TimerContext; > + > typedef struct AwA10PITState { > /*< private >*/ > SysBusDevice parent_obj; > /*< public >*/ > qemu_irq irq[AW_A10_PIT_TIMER_NR]; > ptimer_state * timer[AW_A10_PIT_TIMER_NR]; > + AwA10TimerContext timer_context[AW_A10_PIT_TIMER_NR]; > MemoryRegion iomem; > =20 > uint32_t irq_enable;