From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35271) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPc9s-0006p3-Qh for qemu-devel@nongnu.org; Mon, 17 Mar 2014 14:21:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WPc9n-0004Lh-0W for qemu-devel@nongnu.org; Mon, 17 Mar 2014 14:21:08 -0400 Received: from mail-qg0-x231.google.com ([2607:f8b0:400d:c04::231]:33061) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPc9m-0004Ld-Re for qemu-devel@nongnu.org; Mon, 17 Mar 2014 14:21:02 -0400 Received: by mail-qg0-f49.google.com with SMTP id z60so17682115qgd.8 for ; Mon, 17 Mar 2014 11:21:02 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Mon, 17 Mar 2014 11:20:37 -0700 Message-Id: <1395080443-5853-6-git-send-email-rth@twiddle.net> In-Reply-To: <1395080443-5853-1-git-send-email-rth@twiddle.net> References: <1395080443-5853-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PULL for-2.0 05/11] tcg-sparc: Don't handle remainder List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: blauwirbel@gmail.com, peter.maydell@linaro.org The generic fallback is exactly what we implemented. Signed-off-by: Richard Henderson --- tcg/sparc/tcg-target.c | 21 --------------------- tcg/sparc/tcg-target.h | 4 ++-- 2 files changed, 2 insertions(+), 23 deletions(-) diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c index ebcba71..30a2eaa 100644 --- a/tcg/sparc/tcg-target.c +++ b/tcg/sparc/tcg-target.c @@ -1289,15 +1289,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, tcg_out_div32(s, args[0], args[1], args[2], const_args[2], 1); break; - case INDEX_op_rem_i32: - case INDEX_op_remu_i32: - tcg_out_div32(s, TCG_REG_T1, args[1], args[2], const_args[2], - opc == INDEX_op_remu_i32); - tcg_out_arithc(s, TCG_REG_T1, TCG_REG_T1, args[2], const_args[2], - ARITH_UMUL); - tcg_out_arith(s, args[0], args[1], TCG_REG_T1, ARITH_SUB); - break; - case INDEX_op_brcond_i32: tcg_out_brcond_i32(s, args[2], args[0], args[1], const_args[1], args[3]); @@ -1413,14 +1404,6 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, case INDEX_op_divu_i64: c = ARITH_UDIVX; goto gen_arith; - case INDEX_op_rem_i64: - case INDEX_op_remu_i64: - tcg_out_arithc(s, TCG_REG_T1, args[1], args[2], const_args[2], - opc == INDEX_op_rem_i64 ? ARITH_SDIVX : ARITH_UDIVX); - tcg_out_arithc(s, TCG_REG_T1, TCG_REG_T1, args[2], const_args[2], - ARITH_MULX); - tcg_out_arith(s, args[0], args[1], TCG_REG_T1, ARITH_SUB); - break; case INDEX_op_ext32s_i64: if (const_args[1]) { tcg_out_movi(s, TCG_TYPE_I64, args[0], (int32_t)args[1]); @@ -1484,8 +1467,6 @@ static const TCGTargetOpDef sparc_op_defs[] = { { INDEX_op_mul_i32, { "r", "rZ", "rJ" } }, { INDEX_op_div_i32, { "r", "rZ", "rJ" } }, { INDEX_op_divu_i32, { "r", "rZ", "rJ" } }, - { INDEX_op_rem_i32, { "r", "rZ", "rJ" } }, - { INDEX_op_remu_i32, { "r", "rZ", "rJ" } }, { INDEX_op_sub_i32, { "r", "rZ", "rJ" } }, { INDEX_op_and_i32, { "r", "rZ", "rJ" } }, { INDEX_op_andc_i32, { "r", "rZ", "rJ" } }, @@ -1532,8 +1513,6 @@ static const TCGTargetOpDef sparc_op_defs[] = { { INDEX_op_mul_i64, { "r", "rZ", "rJ" } }, { INDEX_op_div_i64, { "r", "rZ", "rJ" } }, { INDEX_op_divu_i64, { "r", "rZ", "rJ" } }, - { INDEX_op_rem_i64, { "r", "rZ", "rJ" } }, - { INDEX_op_remu_i64, { "r", "rZ", "rJ" } }, { INDEX_op_sub_i64, { "r", "rZ", "rJ" } }, { INDEX_op_and_i64, { "r", "rZ", "rJ" } }, { INDEX_op_andc_i64, { "r", "rZ", "rJ" } }, diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h index 00f3a18..202b88a 100644 --- a/tcg/sparc/tcg-target.h +++ b/tcg/sparc/tcg-target.h @@ -94,7 +94,7 @@ typedef enum { /* optional instructions */ #define TCG_TARGET_HAS_div_i32 1 -#define TCG_TARGET_HAS_rem_i32 1 +#define TCG_TARGET_HAS_rem_i32 0 #define TCG_TARGET_HAS_rot_i32 0 #define TCG_TARGET_HAS_ext8s_i32 0 #define TCG_TARGET_HAS_ext16s_i32 0 @@ -120,7 +120,7 @@ typedef enum { #if TCG_TARGET_REG_BITS == 64 #define TCG_TARGET_HAS_div_i64 1 -#define TCG_TARGET_HAS_rem_i64 1 +#define TCG_TARGET_HAS_rem_i64 0 #define TCG_TARGET_HAS_rot_i64 0 #define TCG_TARGET_HAS_ext8s_i64 0 #define TCG_TARGET_HAS_ext16s_i64 0 -- 1.8.5.3