[Qemu-devel] [PATCH 04/14] tcg-sparc: Support trunc_i32

[Richard Henderson <rth@twiddle.net>]

Unlike a 64-bit shift op, allows the output to be in %l or %i registers
for sparcv8plus.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/sparc/tcg-target.c | 8 ++++++++
 tcg/sparc/tcg-target.h | 2 +-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index 107c1ab..38e8577 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -1476,6 +1476,13 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
     case INDEX_op_ext32u_i64:
         tcg_out_arithi(s, args[0], args[1], 0, SHIFT_SRL);
         break;
+    case INDEX_op_trunc_i32:
+        if (args[2] == 0) {
+            tcg_out_mov(s, TCG_TYPE_I32, args[0], args[1]);
+        } else {
+            tcg_out_arithi(s, args[0], args[1], args[2], SHIFT_SRLX);
+        }
+        break;
 
     case INDEX_op_brcond_i64:
         tcg_out_brcond_i64(s, args[2], args[0], args[1], const_args[1],
@@ -1587,6 +1594,7 @@ static const TCGTargetOpDef sparc_op_defs[] = {
 
     { INDEX_op_ext32s_i64, { "r", "r" } },
     { INDEX_op_ext32u_i64, { "r", "r" } },
+    { INDEX_op_trunc_i32,  { "r", "r" } },
 
     { INDEX_op_brcond_i64, { "rZ", "rJ" } },
     { INDEX_op_setcond_i64, { "r", "rZ", "rJ" } },
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
index 8c3a8a4..7b8b33e 100644
--- a/tcg/sparc/tcg-target.h
+++ b/tcg/sparc/tcg-target.h
@@ -119,7 +119,7 @@ typedef enum {
 #define TCG_TARGET_HAS_mulsh_i32        0
 
 #if TCG_TARGET_REG_BITS == 64
-#define TCG_TARGET_HAS_trunc_i32        0
+#define TCG_TARGET_HAS_trunc_i32        1
 #define TCG_TARGET_HAS_div_i64          1
 #define TCG_TARGET_HAS_rem_i64          0
 #define TCG_TARGET_HAS_rot_i64          0
-- 
1.8.5.3