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From: Peter Maydell <peter.maydell@linaro.org>
To: Anthony Liguori <aliguori@amazon.com>
Cc: "Blue Swirl" <blauwirbel@gmail.com>,
	"Andreas Färber" <andreas.faerber@web.de>,
	qemu-devel@nongnu.org, "Aurelien Jarno" <aurelien@aurel32.net>
Subject: [Qemu-devel] [PULL 09/30] target-arm: A64: Add FSQRT to C3.6.17 (two misc)
Date: Mon, 17 Mar 2014 22:12:00 +0000	[thread overview]
Message-ID: <1395094341-19339-10-git-send-email-peter.maydell@linaro.org> (raw)
In-Reply-To: <1395094341-19339-1-git-send-email-peter.maydell@linaro.org>

From: Alex Bennée <alex.bennee@linaro.org>

Implement FSQRT in the two-reg-misc category.
GCC uses this instruction form.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1394822294-14837-5-git-send-email-peter.maydell@linaro.org
---
 target-arm/translate-a64.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 550decc..427f484 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -6623,6 +6623,9 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
     case 0x6f: /* FNEG */
         gen_helper_vfp_negd(tcg_rd, tcg_rn);
         break;
+    case 0x7f: /* FSQRT */
+        gen_helper_vfp_sqrtd(tcg_rd, tcg_rn, cpu_env);
+        break;
     default:
         g_assert_not_reached();
     }
@@ -8392,6 +8395,12 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
             }
             handle_2misc_fcmp_zero(s, opcode, false, u, is_q, size, rn, rd);
             return;
+        case 0x7f: /* FSQRT */
+            if (size == 3 && !is_q) {
+                unallocated_encoding(s);
+                return;
+            }
+            break;
         case 0x16: /* FCVTN, FCVTN2 */
         case 0x17: /* FCVTL, FCVTL2 */
         case 0x18: /* FRINTN */
@@ -8416,7 +8425,6 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
         case 0x7b: /* FCVTZU */
         case 0x7c: /* URSQRTE */
         case 0x7d: /* FRSQRTE */
-        case 0x7f: /* FSQRT */
             unsupported_encoding(s, insn);
             return;
         default:
@@ -8493,6 +8501,9 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
                 case 0x6f: /* FNEG */
                     gen_helper_vfp_negs(tcg_res, tcg_op);
                     break;
+                case 0x7f: /* FSQRT */
+                    gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env);
+                    break;
                 default:
                     g_assert_not_reached();
                 }
-- 
1.9.0

  parent reply	other threads:[~2014-03-17 22:27 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-03-17 22:11 [Qemu-devel] [PULL for-2.0rc1 00/30] target-arm queue Peter Maydell
2014-03-17 22:11 ` [Qemu-devel] [PULL 01/30] vexpress: Set reset-cbar property for CPUs Peter Maydell
2014-03-17 22:11 ` [Qemu-devel] [PULL 02/30] realview-pbx-a9: " Peter Maydell
2014-03-17 22:11 ` [Qemu-devel] [PULL 03/30] exynos4210: Set reset-cbar property of Cortex-A9 CPUs Peter Maydell
2014-03-17 22:11 ` [Qemu-devel] [PULL 04/30] virt: Set reset-cbar on CPUs Peter Maydell
2014-03-17 22:11 ` [Qemu-devel] [PULL 05/30] target-arm: Add ARM_CP_IO notation to PMCR reginfo Peter Maydell
2014-03-17 22:11 ` [Qemu-devel] [PULL 06/30] target-arm: A64: Implement PMULL instruction Peter Maydell
2014-03-17 22:11 ` [Qemu-devel] [PULL 07/30] target-arm: A64: Fix bug in add_sub_ext handling of rn Peter Maydell
2014-03-17 22:11 ` [Qemu-devel] [PULL 08/30] target-arm: A64: Add last AdvSIMD Integer to FP ops Peter Maydell
2014-03-17 22:12 ` Peter Maydell [this message]
2014-03-17 22:12 ` [Qemu-devel] [PULL 10/30] target-arm: A64: Add remaining CLS/Z vector ops Peter Maydell
2014-03-17 22:12 ` [Qemu-devel] [PULL 11/30] target-arm: A64: Saturating and narrowing shift ops Peter Maydell
2014-03-17 22:12 ` [Qemu-devel] [PULL 12/30] target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALP Peter Maydell
2014-03-17 22:12 ` [Qemu-devel] [PULL 13/30] target-arm: A64: Implement SHLL, SHLL2 Peter Maydell
2014-03-17 22:12 ` [Qemu-devel] [PULL 14/30] target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructions Peter Maydell
2014-03-17 22:12 ` [Qemu-devel] [PULL 15/30] target-arm: A64: Implement FCVTN Peter Maydell
2014-03-17 22:12 ` [Qemu-devel] [PULL 16/30] target-arm: A64: Implement FCVTL Peter Maydell
2014-03-17 22:12 ` [Qemu-devel] [PULL 17/30] target-arm: A64: List unsupported shift-imm opcodes Peter Maydell
2014-03-17 22:12 ` [Qemu-devel] [PULL 18/30] target-arm: A64: Add FRECPX (reciprocal exponent) Peter Maydell
2014-03-17 22:12 ` [Qemu-devel] [PULL 19/30] target-arm: A64: Implement SRI Peter Maydell
2014-03-17 22:12 ` [Qemu-devel] [PULL 20/30] target-arm: A64: Implement FRINT* Peter Maydell
2014-03-17 22:12 ` [Qemu-devel] [PULL 21/30] exec-all.h: Increase MAX_OP_PER_INSTR for ARM A64 decoder Peter Maydell
2014-03-17 22:12 ` [Qemu-devel] [PULL 22/30] target-arm: A64: Handle saturating left shifts SQSHL, SQSHLU, UQSHL Peter Maydell
2014-03-17 22:12 ` [Qemu-devel] [PULL 23/30] target-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categories Peter Maydell
2014-03-17 22:12 ` [Qemu-devel] [PULL 24/30] softfloat: export squash_input_denormal functions Peter Maydell
2014-03-17 22:12 ` [Qemu-devel] [PULL 25/30] target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPE Peter Maydell
2014-03-17 22:12 ` [Qemu-devel] [PULL 26/30] target-arm: A64: Move handle_2misc_narrow function Peter Maydell
2014-03-17 22:12 ` [Qemu-devel] [PULL 27/30] target-arm: A64: Implement scalar saturating narrow ops Peter Maydell
2014-03-17 22:12 ` [Qemu-devel] [PULL 28/30] target-arm: A64: Implement FCVTXN Peter Maydell
2014-03-17 22:12 ` [Qemu-devel] [PULL 29/30] target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate) Peter Maydell
2014-03-17 22:12 ` [Qemu-devel] [PULL 30/30] scripts/qemu-binfmt-conf.sh: Add AArch64 registration Peter Maydell
2014-03-18 16:41 ` [Qemu-devel] [PULL for-2.0rc1 00/30] target-arm queue Peter Maydell

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