From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34401) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPqBp-0005Mp-5T for qemu-devel@nongnu.org; Tue, 18 Mar 2014 05:20:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WPqBj-0001LG-6o for qemu-devel@nongnu.org; Tue, 18 Mar 2014 05:20:05 -0400 Received: from mail-wi0-f171.google.com ([209.85.212.171]:39035) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPqBj-0001LB-19 for qemu-devel@nongnu.org; Tue, 18 Mar 2014 05:19:59 -0400 Received: by mail-wi0-f171.google.com with SMTP id hn9so3345527wib.10 for ; Tue, 18 Mar 2014 02:19:58 -0700 (PDT) From: Alvise Rigo Date: Tue, 18 Mar 2014 10:19:43 +0100 Message-Id: <1395134389-25778-2-git-send-email-a.rigo@virtualopensystems.com> In-Reply-To: <1395134389-25778-1-git-send-email-a.rigo@virtualopensystems.com> References: <1395134389-25778-1-git-send-email-a.rigo@virtualopensystems.com> Subject: [Qemu-devel] [PATCH v2 1/7] target-arm: Decouple AArch64 cp registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , tech@virtualopensystems.com, Alvise Rigo Relying on the AArch64 views for the migration of cp registers values makes impossible to have a successful migration between TCG and KVM because the latter uses the AArch32 indexes format: force the AArch32 processor to not generate the cp registers belonging to the 64bit architecture. Signed-off-by: Alvise Rigo --- target-arm/helper.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/target-arm/helper.c b/target-arm/helper.c index f65cbac..2791dac 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2313,6 +2313,14 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, /* Private utility function for define_one_arm_cp_reg_with_opaque(): * add a single reginfo struct to the hash table. */ + CPUARMState *env = &cpu->env; + int is_a64 = arm_feature(env, ARM_FEATURE_AARCH64); + if (((r->state == ARM_CP_STATE_BOTH && state == ARM_CP_STATE_AA64 + && !is_a64) || (r->state == ARM_CP_STATE_AA64 && !is_a64))) { + /* no need of the AArch64 cp definition */ + return; + } + uint32_t *key = g_new(uint32_t, 1); ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo)); int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0; @@ -2322,9 +2330,12 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, * view handles that. AArch64 also handles reset. * We assume it is a cp15 register. */ + if (is_a64) { + /* this is an AArch64 view */ + r2->type |= ARM_CP_NO_MIGRATE; + r2->resetfn = arm_cp_reset_ignore; + } r2->cp = 15; - r2->type |= ARM_CP_NO_MIGRATE; - r2->resetfn = arm_cp_reset_ignore; #ifdef HOST_WORDS_BIGENDIAN if (r2->fieldoffset) { r2->fieldoffset += sizeof(uint32_t); -- 1.8.3.2