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From: Alvise Rigo <a.rigo@virtualopensystems.com>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
	tech@virtualopensystems.com,
	Alvise Rigo <a.rigo@virtualopensystems.com>
Subject: [Qemu-devel] [PATCH v2 4/7] target-arm: Exclude IC bit from L2CTLR
Date: Tue, 18 Mar 2014 10:19:46 +0100	[thread overview]
Message-ID: <1395134389-25778-5-git-send-email-a.rigo@virtualopensystems.com> (raw)
In-Reply-To: <1395134389-25778-1-git-send-email-a.rigo@virtualopensystems.com>

The real hardware seems to not set the Interrupt Controller bit of the
L2CTLR cp register; on the contrary it could set some other bits
regarding RAM features that are not modelled in TCG, so we can mask them out.

Signed-off-by: Alvise Rigo <a.rigo@virtualopensystems.com>
---
 target-arm/cpu.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 3f0a9b3..434653d 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -685,10 +685,8 @@ static void cortex_a9_initfn(Object *obj)
 #ifndef CONFIG_USER_ONLY
 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 {
-    /* Linux wants the number of processors from here.
-     * Might as well set the interrupt-controller bit too.
-     */
-    return ((smp_cpus - 1) << 24) | (1 << 23);
+    /* Linux wants the number of processors from here. */
+    return (smp_cpus - 1) << 24;
 }
 #endif
 
@@ -741,7 +739,7 @@ static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
 #ifndef CONFIG_USER_ONLY
     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
-      .writefn = arm_cp_write_ignore, },
+      .writefn = arm_cp_write_ignore, .attr_mask = (3 << 24),},
 #endif
     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
-- 
1.8.3.2

  parent reply	other threads:[~2014-03-18  9:20 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-03-18  9:19 [Qemu-devel] [PATCH v2 0/7] target-arm: KVM to TCG migration Alvise Rigo
2014-03-18  9:19 ` [Qemu-devel] [PATCH v2 1/7] target-arm: Decouple AArch64 cp registers Alvise Rigo
2014-03-18  9:19 ` [Qemu-devel] [PATCH v2 2/7] target-arm: Migrate CCSIDR registers Alvise Rigo
2014-03-18  9:19 ` [Qemu-devel] [PATCH v2 3/7] target-arm: Add a way to mask some Alvise Rigo
2014-03-18  9:19 ` Alvise Rigo [this message]
2014-03-18  9:19 ` [Qemu-devel] [PATCH v2 5/7] target-arm: Make TTBR0/1 and TTBRC cp Alvise Rigo
2014-03-18  9:19 ` [Qemu-devel] [PATCH v2 6/7] target-arm: Added ADFSR/AIFSR and REVIDR Alvise Rigo
2014-03-18  9:19 ` [Qemu-devel] [PATCH v2 7/7] target-arm: Minor cp registers changes Alvise Rigo

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