From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34497) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPqBv-0005Zo-Bi for qemu-devel@nongnu.org; Tue, 18 Mar 2014 05:20:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WPqBn-0001TU-AW for qemu-devel@nongnu.org; Tue, 18 Mar 2014 05:20:11 -0400 Received: from mail-wi0-f177.google.com ([209.85.212.177]:40306) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPqBn-0001Rs-4m for qemu-devel@nongnu.org; Tue, 18 Mar 2014 05:20:03 -0400 Received: by mail-wi0-f177.google.com with SMTP id cc10so3366474wib.4 for ; Tue, 18 Mar 2014 02:20:02 -0700 (PDT) From: Alvise Rigo Date: Tue, 18 Mar 2014 10:19:46 +0100 Message-Id: <1395134389-25778-5-git-send-email-a.rigo@virtualopensystems.com> In-Reply-To: <1395134389-25778-1-git-send-email-a.rigo@virtualopensystems.com> References: <1395134389-25778-1-git-send-email-a.rigo@virtualopensystems.com> Subject: [Qemu-devel] [PATCH v2 4/7] target-arm: Exclude IC bit from L2CTLR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , tech@virtualopensystems.com, Alvise Rigo The real hardware seems to not set the Interrupt Controller bit of the L2CTLR cp register; on the contrary it could set some other bits regarding RAM features that are not modelled in TCG, so we can mask them out. Signed-off-by: Alvise Rigo --- target-arm/cpu.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 3f0a9b3..434653d 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -685,10 +685,8 @@ static void cortex_a9_initfn(Object *obj) #ifndef CONFIG_USER_ONLY static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) { - /* Linux wants the number of processors from here. - * Might as well set the interrupt-controller bit too. - */ - return ((smp_cpus - 1) << 24) | (1 << 23); + /* Linux wants the number of processors from here. */ + return (smp_cpus - 1) << 24; } #endif @@ -741,7 +739,7 @@ static const ARMCPRegInfo cortexa15_cp_reginfo[] = { #ifndef CONFIG_USER_ONLY { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2, .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read, - .writefn = arm_cp_write_ignore, }, + .writefn = arm_cp_write_ignore, .attr_mask = (3 << 24),}, #endif { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3, .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, -- 1.8.3.2