From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34521) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPqBy-0005ke-Fn for qemu-devel@nongnu.org; Tue, 18 Mar 2014 05:20:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WPqBr-0001g1-8S for qemu-devel@nongnu.org; Tue, 18 Mar 2014 05:20:14 -0400 Received: from mail-we0-f182.google.com ([74.125.82.182]:51448) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPqBr-0001ev-3F for qemu-devel@nongnu.org; Tue, 18 Mar 2014 05:20:07 -0400 Received: by mail-we0-f182.google.com with SMTP id p61so5680667wes.27 for ; Tue, 18 Mar 2014 02:20:06 -0700 (PDT) From: Alvise Rigo Date: Tue, 18 Mar 2014 10:19:48 +0100 Message-Id: <1395134389-25778-7-git-send-email-a.rigo@virtualopensystems.com> In-Reply-To: <1395134389-25778-1-git-send-email-a.rigo@virtualopensystems.com> References: <1395134389-25778-1-git-send-email-a.rigo@virtualopensystems.com> Subject: [Qemu-devel] [PATCH v2 6/7] target-arm: Added ADFSR/AIFSR and REVIDR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , tech@virtualopensystems.com, Alvise Rigo These registers are required in TCG because they are migrated by KVM: their absence from the cpreg table leads to a migration failure. Signed-off-by: Alvise Rigo --- target-arm/cpu.h | 1 + target-arm/helper.c | 9 +++++++++ 2 files changed, 10 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index adcfa42..2381fc5 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -170,6 +170,7 @@ typedef struct CPUARMState { /* System control coprocessor (cp15) */ struct { uint32_t c0_cpuid; + uint32_t c0_revid; uint64_t c0_cssel; /* Cache size selection. */ uint64_t c1_sys; /* System control register. */ uint64_t c1_coproc; /* Coprocessor access register. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index daa707e..1fec33a 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1456,6 +1456,10 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c5_insn), .resetvalue = 0, }, + { .name = "ADFSR", .cp = 15, .crn = 5, .crm = 1, .opc1 = 0, .opc2 = 0, + .access = PL1_R, .resetvalue = 0, .type = ARM_CP_CONST, }, + { .name = "AIFSR", .cp = 15, .crn = 5, .crm = 1, .opc1 = 0, .opc2 = 1, + .access = PL1_R, .resetvalue = 0, .type = ARM_CP_CONST, }, { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1), @@ -2148,6 +2152,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) .writefn = arm_cp_write_ignore, .raw_writefn = raw_write, .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid), .type = ARM_CP_OVERRIDE }, + { .name = "REVIDR", + .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 6, + .access = PL1_R, .resetvalue = 0, + .writefn = arm_cp_write_ignore, .raw_writefn = raw_write, + .fieldoffset = offsetof(CPUARMState, cp15.c0_revid),}, { .name = "MIDR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .opc2 = 0, .crn = 0, .crm = 0, .access = PL1_R, .resetvalue = cpu->midr, .type = ARM_CP_CONST }, -- 1.8.3.2