[Qemu-devel] [PATCH v2 7/7] target-arm: Minor cp registers changes

[Alvise Rigo <a.rigo@virtualopensystems.com>]

Minor changes still required to enable KVM -> TCG migration:
    * The MPIDR register is now migrated, as KVM does.
    * Implemented the SMP bit of the AUXCR register, the other bits are
      masked through attr_mask because not supported.
    * Added the attr_mask to ID_PFR0 to exclude the Jazelle bits (in TCG
      these bits are set in the reset value of the register, probably
      we should consider to remove them).

Signed-off-by: Alvise Rigo <a.rigo@virtualopensystems.com>
---
 target-arm/helper.c | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/target-arm/helper.c b/target-arm/helper.c
index 1fec33a..ee73ad7 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1660,7 +1660,7 @@ static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
     { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
-      .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE },
+      .access = PL1_R, .readfn = mpidr_read },
     REGINFO_SENTINEL
 };
 
@@ -1911,6 +1911,16 @@ static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
     return CP_ACCESS_OK;
 }
 
+static uint64_t auxcr_reg_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    if (smp_cpus > 1) {
+        /* set the SMP bit accordingly with the number of CPUs */
+        return 1 << 6;
+    }
+
+    return 0;
+}
+
 static void define_aarch64_debug_regs(ARMCPU *cpu)
 {
     /* Define breakpoint and watchpoint registers. These do nothing
@@ -1957,7 +1967,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
         ARMCPRegInfo v6_idregs[] = {
             { .name = "ID_PFR0", .cp = 15, .crn = 0, .crm = 1,
               .opc1 = 0, .opc2 = 0, .access = PL1_R, .type = ARM_CP_CONST,
-              .resetvalue = cpu->id_pfr0 },
+              .resetvalue = cpu->id_pfr0, .attr_mask = ~(0xF << 8)},
             { .name = "ID_PFR1", .cp = 15, .crn = 0, .crm = 1,
               .opc1 = 0, .opc2 = 1, .access = PL1_R, .type = ARM_CP_CONST,
               .resetvalue = cpu->id_pfr1 },
@@ -2219,8 +2229,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
     if (arm_feature(env, ARM_FEATURE_AUXCR)) {
         ARMCPRegInfo auxcr = {
             .name = "AUXCR", .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1,
-            .access = PL1_RW, .type = ARM_CP_CONST,
-            .resetvalue = cpu->reset_auxcr
+            .access = PL1_RW, .resetvalue = 0, .readfn = auxcr_reg_read,
+            .writefn = arm_cp_write_ignore, .attr_mask = (1 << 6),
         };
         define_one_arm_cp_reg(cpu, &auxcr);
     }
-- 
1.8.3.2