From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54879) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPybM-0005yU-W4 for qemu-devel@nongnu.org; Tue, 18 Mar 2014 14:19:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WPybF-0006xy-Ht for qemu-devel@nongnu.org; Tue, 18 Mar 2014 14:19:00 -0400 Received: from mail-oa0-x22a.google.com ([2607:f8b0:4003:c02::22a]:64865) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPybF-0006x9-DD for qemu-devel@nongnu.org; Tue, 18 Mar 2014 14:18:53 -0400 Received: by mail-oa0-f42.google.com with SMTP id i4so7414138oah.15 for ; Tue, 18 Mar 2014 11:18:52 -0700 (PDT) From: Rob Herring Date: Tue, 18 Mar 2014 13:18:39 -0500 Message-Id: <1395166721-15716-2-git-send-email-robherring2@gmail.com> In-Reply-To: <1395166721-15716-1-git-send-email-robherring2@gmail.com> References: <1395166721-15716-1-git-send-email-robherring2@gmail.com> Subject: [Qemu-devel] [PATCH v3 1/3] pl011: reset the fifo when enabled or disabled List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, Peter Maydell Cc: Rob Herring From: Rob Herring Intermittent issues have been seen where no serial input occurs. It appears the pl011 gets in a state where the rx interrupt never fires because the rx interrupt only asserts when crossing the fifo trigger level. The fifo state appears to get out of sync when the pl011 is re-configured. This combined with the rx timeout interrupt not being modeled results in no more rx interrupts. Disabling the fifo is the recommended way to clear the tx fifo in the TRM (section 3.3.8). The behavior in this case for the rx fifo is undefined in the TRM, but having fifo contents to be maintained during configuration changes is not likely expected behavior. Reseting the fifo state when the fifo size is changed is the simplest solution. Signed-off-by: Rob Herring --- hw/char/pl011.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index a8ae6f4..8103e2e 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -162,6 +162,11 @@ static void pl011_write(void *opaque, hwaddr offset, s->fbrd = value; break; case 11: /* UARTLCR_H */ + /* Reset the FIFO state on FIFO enable or disable */ + if ((s->lcr ^ value) & 0x10) { + s->read_count = 0; + s->read_pos = 0; + } s->lcr = value; pl011_set_read_trigger(s); break; -- 1.8.3.2