From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54895) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPybO-0005yY-59 for qemu-devel@nongnu.org; Tue, 18 Mar 2014 14:19:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WPybH-0006yk-FA for qemu-devel@nongnu.org; Tue, 18 Mar 2014 14:19:02 -0400 Received: from mail-ob0-x235.google.com ([2607:f8b0:4003:c01::235]:61024) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WPybH-0006yg-AJ for qemu-devel@nongnu.org; Tue, 18 Mar 2014 14:18:55 -0400 Received: by mail-ob0-f181.google.com with SMTP id wp4so7253930obc.40 for ; Tue, 18 Mar 2014 11:18:54 -0700 (PDT) From: Rob Herring Date: Tue, 18 Mar 2014 13:18:41 -0500 Message-Id: <1395166721-15716-4-git-send-email-robherring2@gmail.com> In-Reply-To: <1395166721-15716-1-git-send-email-robherring2@gmail.com> References: <1395166721-15716-1-git-send-email-robherring2@gmail.com> Subject: [Qemu-devel] [PATCH v3 3/3] pl011: fix incorrect logic to set the RXFF flag List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, Peter Maydell Cc: Rob Herring From: Rob Herring The receive fifo full bit should be set when 1 character is received and the fifo is disabled or when 16 characters are in the fifo. Signed-off-by: Rob Herring Reviewed-by: Peter Maydell --- hw/char/pl011.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 11c3a75..644aad7 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -221,7 +221,7 @@ static void pl011_put_fifo(void *opaque, uint32_t value) s->read_fifo[slot] = value; s->read_count++; s->flags &= ~PL011_FLAG_RXFE; - if (s->cr & 0x10 || s->read_count == 16) { + if (!(s->lcr & 0x10) || s->read_count == 16) { s->flags |= PL011_FLAG_RXFF; } if (s->read_count == s->read_trigger) { -- 1.8.3.2