From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33772) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WQ1ay-0003QY-Fd for qemu-devel@nongnu.org; Tue, 18 Mar 2014 17:30:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WQ1at-0007u7-OH for qemu-devel@nongnu.org; Tue, 18 Mar 2014 17:30:48 -0400 Received: from mail-pb0-x22e.google.com ([2607:f8b0:400e:c01::22e]:35845) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WQ1at-0007u1-Hm for qemu-devel@nongnu.org; Tue, 18 Mar 2014 17:30:43 -0400 Received: by mail-pb0-f46.google.com with SMTP id rq2so7852529pbb.19 for ; Tue, 18 Mar 2014 14:30:42 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Tue, 18 Mar 2014 14:30:32 -0700 Message-Id: <1395178235-29056-2-git-send-email-rth@twiddle.net> In-Reply-To: <1395178235-29056-1-git-send-email-rth@twiddle.net> References: <1395178235-29056-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v2 1/4] tcg: Use "unspecified behavior" for shifts List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org Change the definition such that shifts are not allowed to crash for any input. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- tcg/README | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/tcg/README b/tcg/README index f178212..776e925 100644 --- a/tcg/README +++ b/tcg/README @@ -36,6 +36,12 @@ or a memory location which is stored in a register outside QEMU TBs A TCG "basic block" corresponds to a list of instructions terminated by a branch instruction. +An operation with "undefined behavior" may result in a crash. + +An operation with "unspecified behavior" shall not crash. However, +the result may be one of several possibilities so may be considered +an "undefined result". + 3) Intermediate representation 3.1) Introduction @@ -239,23 +245,25 @@ t0=t1|~t2 * shl_i32/i64 t0, t1, t2 -t0=t1 << t2. Undefined behavior if t2 < 0 or t2 >= 32 (resp 64) +t0=t1 << t2. Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64) * shr_i32/i64 t0, t1, t2 -t0=t1 >> t2 (unsigned). Undefined behavior if t2 < 0 or t2 >= 32 (resp 64) +t0=t1 >> t2 (unsigned). Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64) * sar_i32/i64 t0, t1, t2 -t0=t1 >> t2 (signed). Undefined behavior if t2 < 0 or t2 >= 32 (resp 64) +t0=t1 >> t2 (signed). Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64) * rotl_i32/i64 t0, t1, t2 -Rotation of t2 bits to the left. Undefined behavior if t2 < 0 or t2 >= 32 (resp 64) +Rotation of t2 bits to the left. +Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64) * rotr_i32/i64 t0, t1, t2 -Rotation of t2 bits to the right. Undefined behavior if t2 < 0 or t2 >= 32 (resp 64) +Rotation of t2 bits to the right. +Unspecified behavior if t2 < 0 or t2 >= 32 (resp 64) ********* Misc -- 1.8.5.3