[Qemu-devel] [PATCH v5 0/3] spapr: fix H_SET_MODE

[Qemu-devel] [PATCH v5 0/3] spapr: fix H_SET_MODE

[Alexey Kardashevskiy]

This fixes H_SET_MODE.
Changes:
v5:
* fixed code style

v4:
* rebased on top of current ppc-next.
* changed PPC2_ISA207S flag value


Alexey Kardashevskiy (3):
  target-ppc: introduce powerisa-207-server flag
  spapr_hcall: fix little-endian resource handling in H_SET_MODE
  spapr_hcall: add address-translation-mode-on-interrupt resource in
    H_SET_MODE

 hw/ppc/spapr_hcall.c        | 67 +++++++++++++++++++++++++++++++++++++++------
 include/hw/ppc/spapr.h      |  9 ++++--
 target-ppc/cpu.h            |  4 +++
 target-ppc/translate_init.c |  3 +-
 4 files changed, 72 insertions(+), 11 deletions(-)

-- 
1.8.4.rc4

[Qemu-devel] [PATCH v5 1/3] target-ppc: introduce powerisa-207-server flag

[Alexey Kardashevskiy]

This flag will be used to decide whether to emulate some bits of
H_SET_MODE hypercall because some are POWER8-only.

While we are here, add 2.05 flag to POWER8 family too. POWER7/7+ already
have it.

Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
 target-ppc/cpu.h            | 2 ++
 target-ppc/translate_init.c | 3 ++-
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 91b7ae5..72cb546 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1900,6 +1900,8 @@ enum {
     PPC2_LSQ_ISA207    = 0x0000000000002000ULL,
     /* ISA 2.07 Altivec                                                      */
     PPC2_ALTIVEC_207   = 0x0000000000004000ULL,
+    /* PowerISA 2.07 Book3s specification                                    */
+    PPC2_ISA207S       = 0x0000000000008000ULL,
 
 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
                         PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 6084f40..6d01c9d 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -7173,7 +7173,8 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
                         PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
                         PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
                         PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
-                        PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207;
+                        PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
+                        PPC2_ISA205 | PPC2_ISA207S;
     pcc->msr_mask = 0x800000000284FF36ULL;
     pcc->mmu_model = POWERPC_MMU_2_06;
 #if defined(CONFIG_SOFTMMU)
-- 
1.8.4.rc4

[Qemu-devel] [PATCH v5 2/3] spapr_hcall: fix little-endian resource handling in H_SET_MODE

[Alexey Kardashevskiy]

This changes resource code definitions to ones used in the host kernel.

This fixes H_SET_MODE_RESOURCE_LE (switch between big endian and
little endian) to sync registers from KVM before changing LPCR value.

This adds a set_spr() helper to update an SPR in a CPU's context to avoid
possible races and makes use of it to change LPCR.

Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
Changes:
v5:
* fixed code design style
---
 hw/ppc/spapr_hcall.c   | 41 +++++++++++++++++++++++++++++++++--------
 include/hw/ppc/spapr.h |  9 +++++++--
 2 files changed, 40 insertions(+), 10 deletions(-)

diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index e999bba..fc5211b 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -4,6 +4,36 @@
 #include "hw/ppc/spapr.h"
 #include "mmu-hash64.h"
 
+struct SPRSyncState {
+    CPUState *cs;
+    int spr;
+    target_ulong value;
+    target_ulong mask;
+};
+
+static void do_spr_sync(void *arg)
+{
+    struct SPRSyncState *s = arg;
+    PowerPCCPU *cpu = POWERPC_CPU(s->cs);
+    CPUPPCState *env = &cpu->env;
+
+    cpu_synchronize_state(s->cs);
+    env->spr[s->spr] &= ~s->mask;
+    env->spr[s->spr] |= s->value;
+}
+
+static void set_spr(CPUState *cs, int spr, target_ulong value,
+                    target_ulong mask)
+{
+    struct SPRSyncState s = {
+        .cs = cs,
+        .spr = spr,
+        .value = value,
+        .mask = mask
+    };
+    run_on_cpu(cs, do_spr_sync, &s);
+}
+
 static target_ulong compute_tlbie_rb(target_ulong v, target_ulong r,
                                      target_ulong pte_index)
 {
@@ -690,7 +720,7 @@ static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPREnvironment *spapr,
     target_ulong value2 = args[3];
     target_ulong ret = H_P2;
 
-    if (resource == H_SET_MODE_ENDIAN) {
+    if (resource == H_SET_MODE_RESOURCE_LE) {
         if (value1) {
             ret = H_P3;
             goto out;
@@ -699,22 +729,17 @@ static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPREnvironment *spapr,
             ret = H_P4;
             goto out;
         }
-
         switch (mflags) {
         case H_SET_MODE_ENDIAN_BIG:
             CPU_FOREACH(cs) {
-                PowerPCCPU *cp = POWERPC_CPU(cs);
-                CPUPPCState *env = &cp->env;
-                env->spr[SPR_LPCR] &= ~LPCR_ILE;
+                set_spr(cs, SPR_LPCR, 0, LPCR_ILE);
             }
             ret = H_SUCCESS;
             break;
 
         case H_SET_MODE_ENDIAN_LITTLE:
             CPU_FOREACH(cs) {
-                PowerPCCPU *cp = POWERPC_CPU(cs);
-                CPUPPCState *env = &cp->env;
-                env->spr[SPR_LPCR] |= LPCR_ILE;
+                set_spr(cs, SPR_LPCR, LPCR_ILE, LPCR_ILE);
             }
             ret = H_SUCCESS;
             break;
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 449fc7c..5fdac1e 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -153,8 +153,13 @@ typedef struct sPAPREnvironment {
 #define H_PP1             (1ULL<<(63-62))
 #define H_PP2             (1ULL<<(63-63))
 
-/* H_SET_MODE flags */
-#define H_SET_MODE_ENDIAN        4
+/* Values for 2nd argument to H_SET_MODE */
+#define H_SET_MODE_RESOURCE_SET_CIABR           1
+#define H_SET_MODE_RESOURCE_SET_DAWR            2
+#define H_SET_MODE_RESOURCE_ADDR_TRANS_MODE     3
+#define H_SET_MODE_RESOURCE_LE                  4
+
+/* Flags for H_SET_MODE_RESOURCE_LE */
 #define H_SET_MODE_ENDIAN_BIG    0
 #define H_SET_MODE_ENDIAN_LITTLE 1
 
-- 
1.8.4.rc4

[Qemu-devel] [PATCH v5 3/3] spapr_hcall: add address-translation-mode-on-interrupt resource in H_SET_MODE

[Alexey Kardashevskiy]

This adds handling of the RESOURCE_ADDR_TRANS_MODE resource from
the H_SET_MODE, for POWER8 (PowerISA 2.07) only.

Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
---
 hw/ppc/spapr_hcall.c | 26 ++++++++++++++++++++++++++
 target-ppc/cpu.h     |  2 ++
 2 files changed, 28 insertions(+)

diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index fc5211b..fb23730 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -747,6 +747,32 @@ static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPREnvironment *spapr,
         default:
             ret = H_UNSUPPORTED_FLAG;
         }
+    } else if (resource == H_SET_MODE_RESOURCE_ADDR_TRANS_MODE) {
+        PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
+
+        if (!(pcc->insns_flags2 & PPC2_ISA207S)) {
+            return H_P2;
+        }
+        if (value1) {
+            ret = H_P3;
+            goto out;
+        }
+        if (value2) {
+            ret = H_P4;
+            goto out;
+        }
+        switch (mflags) {
+        case 0:
+        case 2:
+        case 3:
+            CPU_FOREACH(cs) {
+                set_spr(cs, SPR_LPCR, mflags << LPCR_AIL_SH, LPCR_AIL);
+            }
+            return H_SUCCESS;
+
+        default:
+            return H_UNSUPPORTED_FLAG;
+        }
     }
 
 out:
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 72cb546..577193a 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -462,6 +462,8 @@ struct ppc_slb_t {
 #define MSR_LE   0  /* Little-endian mode                           1 hflags */
 
 #define LPCR_ILE (1 << (63-38))
+#define LPCR_AIL      0x01800000      /* Alternate interrupt location */
+#define LPCR_AIL_SH   (63-40)
 
 #define msr_sf   ((env->msr >> MSR_SF)   & 1)
 #define msr_isf  ((env->msr >> MSR_ISF)  & 1)
-- 
1.8.4.rc4

Re: [Qemu-devel] [PATCH v5 3/3] spapr_hcall: add address-translation-mode-on-interrupt resource in H_SET_MODE

[Mike Day]

Alexey Kardashevskiy <aik@ozlabs.ru> writes:

> This adds handling of the RESOURCE_ADDR_TRANS_MODE resource from
> the H_SET_MODE, for POWER8 (PowerISA 2.07) only.
>
> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: Mike Day <ncmike@ncultra.org>
> ---
>  hw/ppc/spapr_hcall.c | 26 ++++++++++++++++++++++++++
>  target-ppc/cpu.h     |  2 ++
>  2 files changed, 28 insertions(+)
>
> diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
> index fc5211b..fb23730 100644
> --- a/hw/ppc/spapr_hcall.c
> +++ b/hw/ppc/spapr_hcall.c
> @@ -747,6 +747,32 @@ static target_ulong h_set_mode(PowerPCCPU *cpu, sPAPREnvironment *spapr,
>          default:
>              ret = H_UNSUPPORTED_FLAG;
>          }
> +    } else if (resource == H_SET_MODE_RESOURCE_ADDR_TRANS_MODE) {
> +        PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
> +
> +        if (!(pcc->insns_flags2 & PPC2_ISA207S)) {
> +            return H_P2;
               
               ret = H_P2;
               goto out; 
               
Just a nit to make for easier review. The above would be more
consistent. (Even though ret is already initialized to H_P2.)

> +        }
> +        if (value1) {
> +            ret = H_P3;
> +            goto out;
> +        }
> +        if (value2) {
> +            ret = H_P4;
> +            goto out;
> +        }
> +        switch (mflags) {
> +        case 0:
> +        case 2:
> +        case 3:
> +            CPU_FOREACH(cs) {
> +                set_spr(cs, SPR_LPCR, mflags << LPCR_AIL_SH, LPCR_AIL);
> +            }
> +            return H_SUCCESS;
> +
> +        default:
> +            return H_UNSUPPORTED_FLAG;
> +        }
>      }
>  
>  out:
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 72cb546..577193a 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -462,6 +462,8 @@ struct ppc_slb_t {
>  #define MSR_LE   0  /* Little-endian mode                           1 hflags */
>  
>  #define LPCR_ILE (1 << (63-38))
> +#define LPCR_AIL      0x01800000      /* Alternate interrupt location */
> +#define LPCR_AIL_SH   (63-40)
>  
>  #define msr_sf   ((env->msr >> MSR_SF)   & 1)
>  #define msr_isf  ((env->msr >> MSR_ISF)  & 1)
> -- 
> 1.8.4.rc4
>
>

-- 
Mike Day | "Endurance is a Virtue"

Re: [Qemu-devel] [PATCH v5 0/3] spapr: fix H_SET_MODE

[Andreas Färber]

Am 20.03.2014 01:03, schrieb Alexey Kardashevskiy:
> This fixes H_SET_MODE.
> Changes:
> v5:
> * fixed code style
> 
> v4:
> * rebased on top of current ppc-next.
> * changed PPC2_ISA207S flag value
> 
> 
> Alexey Kardashevskiy (3):
>   target-ppc: introduce powerisa-207-server flag
>   spapr_hcall: fix little-endian resource handling in H_SET_MODE

Thanks, applied these two to my ppc-next:
https://github.com/afaerber/qemu-cpu/commits/ppc-next

>   spapr_hcall: add address-translation-mode-on-interrupt resource in
>     H_SET_MODE

This doesn't strike me as a bug fix worthy of -rc1? Does anything
severely break without it that would justify putting it in -rc2?

Also some additional reviewer would assure me there's been no oversight.

Regards,
Andreas

>  hw/ppc/spapr_hcall.c        | 67 +++++++++++++++++++++++++++++++++++++++------
>  include/hw/ppc/spapr.h      |  9 ++++--
>  target-ppc/cpu.h            |  4 +++
>  target-ppc/translate_init.c |  3 +-
>  4 files changed, 72 insertions(+), 11 deletions(-)

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