From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33787) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WQkTX-0008Qn-DG for qemu-devel@nongnu.org; Thu, 20 Mar 2014 17:26:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WQkTS-0003ul-J4 for qemu-devel@nongnu.org; Thu, 20 Mar 2014 17:26:07 -0400 Received: from mail-ee0-x235.google.com ([2a00:1450:4013:c00::235]:44596) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WQkTS-0003uc-C2 for qemu-devel@nongnu.org; Thu, 20 Mar 2014 17:26:02 -0400 Received: by mail-ee0-f53.google.com with SMTP id b57so1135429eek.40 for ; Thu, 20 Mar 2014 14:26:01 -0700 (PDT) From: Beniamino Galvani Date: Thu, 20 Mar 2014 22:25:13 +0100 Message-Id: <1395350719-3778-2-git-send-email-b.galvani@gmail.com> In-Reply-To: <1395350719-3778-1-git-send-email-b.galvani@gmail.com> References: <1395350719-3778-1-git-send-email-b.galvani@gmail.com> Subject: [Qemu-devel] [PATCH v4 1/7] allwinner-a10-pic: set vector address when an interrupt is pending List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Beniamino Galvani , Peter Maydell , Peter Crosthwaite , Li Guang This patch implements proper updating of the vector register which should hold, according to the A10 user manual, the vector address for the interrupt currently active on the CPU IRQ input. Interrupt priority is not implemented at the moment and thus the first pending interrupt is returned. Signed-off-by: Beniamino Galvani Reviewed-by: Peter Crosthwaite Reviewed-by: Li Guang --- hw/intc/allwinner-a10-pic.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c index 407d563..00f3c11 100644 --- a/hw/intc/allwinner-a10-pic.c +++ b/hw/intc/allwinner-a10-pic.c @@ -23,11 +23,20 @@ static void aw_a10_pic_update(AwA10PICState *s) { uint8_t i; - int irq = 0, fiq = 0; + int irq = 0, fiq = 0, pending; + + s->vector = 0; for (i = 0; i < AW_A10_PIC_REG_NUM; i++) { irq |= s->irq_pending[i] & ~s->mask[i]; fiq |= s->select[i] & s->irq_pending[i] & ~s->mask[i]; + + if (!s->vector) { + pending = ffs(s->irq_pending[i] & ~s->mask[i]); + if (pending) { + s->vector = (i * 32 + pending - 1) * 4; + } + } } qemu_set_irq(s->parent_irq, !!irq); @@ -84,9 +93,6 @@ static void aw_a10_pic_write(void *opaque, hwaddr offset, uint64_t value, uint8_t index = (offset & 0xc) / 4; switch (offset) { - case AW_A10_PIC_VECTOR: - s->vector = value & ~0x3; - break; case AW_A10_PIC_BASE_ADDR: s->base_addr = value & ~0x3; case AW_A10_PIC_PROTECT: -- 1.7.10.4