From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33814) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WQkTZ-0008Us-F0 for qemu-devel@nongnu.org; Thu, 20 Mar 2014 17:26:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WQkTT-0003uz-Vp for qemu-devel@nongnu.org; Thu, 20 Mar 2014 17:26:09 -0400 Received: from mail-ee0-x22b.google.com ([2a00:1450:4013:c00::22b]:49115) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WQkTT-0003ur-Oe for qemu-devel@nongnu.org; Thu, 20 Mar 2014 17:26:03 -0400 Received: by mail-ee0-f43.google.com with SMTP id e53so1146316eek.30 for ; Thu, 20 Mar 2014 14:26:03 -0700 (PDT) From: Beniamino Galvani Date: Thu, 20 Mar 2014 22:25:14 +0100 Message-Id: <1395350719-3778-3-git-send-email-b.galvani@gmail.com> In-Reply-To: <1395350719-3778-1-git-send-email-b.galvani@gmail.com> References: <1395350719-3778-1-git-send-email-b.galvani@gmail.com> Subject: [Qemu-devel] [PATCH v4 2/7] allwinner-a10-pic: fix behaviour of pending register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Beniamino Galvani , Peter Maydell , Peter Crosthwaite , Li Guang The pending register is read-only and the value returned upon a read reflects the state of irq input pins (interrupts are level triggered). This patch implements such behaviour. Signed-off-by: Beniamino Galvani Reviewed-by: Li Guang Reviewed-by: Peter Crosthwaite --- hw/intc/allwinner-a10-pic.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/intc/allwinner-a10-pic.c b/hw/intc/allwinner-a10-pic.c index 00f3c11..0924d98 100644 --- a/hw/intc/allwinner-a10-pic.c +++ b/hw/intc/allwinner-a10-pic.c @@ -49,6 +49,8 @@ static void aw_a10_pic_set_irq(void *opaque, int irq, int level) if (level) { set_bit(irq % 32, (void *)&s->irq_pending[irq / 32]); + } else { + clear_bit(irq % 32, (void *)&s->irq_pending[irq / 32]); } aw_a10_pic_update(s); } @@ -102,7 +104,11 @@ static void aw_a10_pic_write(void *opaque, hwaddr offset, uint64_t value, s->nmi = value; break; case AW_A10_PIC_IRQ_PENDING ... AW_A10_PIC_IRQ_PENDING + 8: - s->irq_pending[index] &= ~value; + /* + * The register is read-only; nevertheless, Linux (including + * the version originally shipped by Allwinner) pretends to + * write to the register. Just ignore it. + */ break; case AW_A10_PIC_FIQ_PENDING ... AW_A10_PIC_FIQ_PENDING + 8: s->fiq_pending[index] &= ~value; -- 1.7.10.4