From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33902) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WQkTd-0000Bz-A9 for qemu-devel@nongnu.org; Thu, 20 Mar 2014 17:26:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WQkTX-0003vj-GB for qemu-devel@nongnu.org; Thu, 20 Mar 2014 17:26:13 -0400 Received: from mail-ee0-x22d.google.com ([2a00:1450:4013:c00::22d]:51862) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WQkTX-0003vV-AE for qemu-devel@nongnu.org; Thu, 20 Mar 2014 17:26:07 -0400 Received: by mail-ee0-f45.google.com with SMTP id d17so1146369eek.4 for ; Thu, 20 Mar 2014 14:26:06 -0700 (PDT) From: Beniamino Galvani Date: Thu, 20 Mar 2014 22:25:16 +0100 Message-Id: <1395350719-3778-5-git-send-email-b.galvani@gmail.com> In-Reply-To: <1395350719-3778-1-git-send-email-b.galvani@gmail.com> References: <1395350719-3778-1-git-send-email-b.galvani@gmail.com> Subject: [Qemu-devel] [PATCH v4 4/7] allwinner-a10-pit: use level triggered interrupts List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Beniamino Galvani , Peter Maydell , Peter Crosthwaite , Li Guang Convert the interrupt generation logic to the use of level triggered interrupts. Signed-off-by: Beniamino Galvani Reviewed-by: Peter Crosthwaite --- hw/timer/allwinner-a10-pit.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index 696b7d9..5aa78a9 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -19,6 +19,15 @@ #include "sysemu/sysemu.h" #include "hw/timer/allwinner-a10-pit.h" +static void a10_pit_update_irq(AwA10PITState *s) +{ + int i; + + for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { + qemu_set_irq(s->irq[i], !!(s->irq_status & s->irq_enable & (1 << i))); + } +} + static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) { AwA10PITState *s = AW_A10_PIT(opaque); @@ -74,9 +83,11 @@ static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, switch (offset) { case AW_A10_PIT_TIMER_IRQ_EN: s->irq_enable = value; + a10_pit_update_irq(s); break; case AW_A10_PIT_TIMER_IRQ_ST: s->irq_status &= ~value; + a10_pit_update_irq(s); break; case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END: index = offset & 0xf0; @@ -178,6 +189,8 @@ static void a10_pit_reset(DeviceState *dev) s->irq_enable = 0; s->irq_status = 0; + a10_pit_update_irq(s); + for (i = 0; i < 6; i++) { s->control[i] = AW_A10_PIT_DEFAULT_CLOCK; s->interval[i] = 0; @@ -203,7 +216,7 @@ static void a10_pit_timer_cb(void *opaque) ptimer_stop(s->timer[i]); s->control[i] &= ~AW_A10_PIT_TIMER_EN; } - qemu_irq_pulse(s->irq[i]); + a10_pit_update_irq(s); } } -- 1.7.10.4