* [Qemu-devel] [PULL 1/2] target-arm: Fix A64 Neon MLS
2014-03-24 17:18 [Qemu-devel] [PULL for-2.0 0/2] target-arm queue Peter Maydell
@ 2014-03-24 17:18 ` Peter Maydell
2014-03-24 17:18 ` [Qemu-devel] [PULL 2/2] target-arm: Load ELF images with the correct machine type for CPU Peter Maydell
2014-03-24 20:21 ` [Qemu-devel] [PULL for-2.0 0/2] target-arm queue Peter Maydell
2 siblings, 0 replies; 4+ messages in thread
From: Peter Maydell @ 2014-03-24 17:18 UTC (permalink / raw)
To: Anthony Liguori; +Cc: Blue Swirl, qemu-devel, Aurelien Jarno
The order of operands for the accumulate step in disas_simd_3same_int()
was reversed. This only affected the MLS instruction, since all the
other accumulating instructions in this category perform an addition
rather than a subtraction.
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target-arm/translate-a64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 9f06450..9175e48 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -8925,7 +8925,7 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
genfn = fns[size][is_sub];
read_vec_element_i32(s, tcg_op1, rd, pass, MO_32);
- genfn(tcg_res, tcg_res, tcg_op1);
+ genfn(tcg_res, tcg_op1, tcg_res);
}
write_vec_element_i32(s, tcg_res, rd, pass, MO_32);
--
1.9.0
^ permalink raw reply related [flat|nested] 4+ messages in thread* [Qemu-devel] [PULL 2/2] target-arm: Load ELF images with the correct machine type for CPU
2014-03-24 17:18 [Qemu-devel] [PULL for-2.0 0/2] target-arm queue Peter Maydell
2014-03-24 17:18 ` [Qemu-devel] [PULL 1/2] target-arm: Fix A64 Neon MLS Peter Maydell
@ 2014-03-24 17:18 ` Peter Maydell
2014-03-24 20:21 ` [Qemu-devel] [PULL for-2.0 0/2] target-arm queue Peter Maydell
2 siblings, 0 replies; 4+ messages in thread
From: Peter Maydell @ 2014-03-24 17:18 UTC (permalink / raw)
To: Anthony Liguori; +Cc: Blue Swirl, qemu-devel, Aurelien Jarno
When trying to load an ELF file specified via -kernel, we need to
pass load_elf() the ELF machine type corresponding to the CPU we're
booting with, not the one corresponding to the softmmu binary
we happen to be running. (The two are different in the case of
loading a 32-bit ARM ELF file into a 32 bit CPU being emulated
by qemu-system aarch64.) This was causing us to incorrectly fail
to load ELF images in this situation.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Message-id: 1395427476-25546-1-git-send-email-peter.maydell@linaro.org
---
hw/arm/boot.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index dc62918..3d1f4a2 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -448,6 +448,7 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
int initrd_size;
int is_linux = 0;
uint64_t elf_entry;
+ int elf_machine;
hwaddr entry, kernel_load_offset;
int big_endian;
static const ARMInsnFixup *primary_loader;
@@ -463,9 +464,11 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
primary_loader = bootloader_aarch64;
kernel_load_offset = KERNEL64_LOAD_ADDR;
+ elf_machine = EM_AARCH64;
} else {
primary_loader = bootloader;
kernel_load_offset = KERNEL_LOAD_ADDR;
+ elf_machine = EM_ARM;
}
info->dtb_filename = qemu_opt_get(qemu_get_machine_opts(), "dtb");
@@ -501,7 +504,7 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
/* Assume that raw images are linux kernels, and ELF images are not. */
kernel_size = load_elf(info->kernel_filename, NULL, NULL, &elf_entry,
- NULL, NULL, big_endian, ELF_MACHINE, 1);
+ NULL, NULL, big_endian, elf_machine, 1);
entry = elf_entry;
if (kernel_size < 0) {
kernel_size = load_uimage(info->kernel_filename, &entry, NULL,
--
1.9.0
^ permalink raw reply related [flat|nested] 4+ messages in thread