From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48917) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WSW0K-00078m-MZ for qemu-devel@nongnu.org; Tue, 25 Mar 2014 14:23:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WSW0E-0004DS-RJ for qemu-devel@nongnu.org; Tue, 25 Mar 2014 14:23:16 -0400 Received: from mail-ee0-x22e.google.com ([2a00:1450:4013:c00::22e]:40174) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WSW0E-0004DB-KY for qemu-devel@nongnu.org; Tue, 25 Mar 2014 14:23:10 -0400 Received: by mail-ee0-f46.google.com with SMTP id t10so774158eei.33 for ; Tue, 25 Mar 2014 11:23:09 -0700 (PDT) From: Beniamino Galvani Date: Tue, 25 Mar 2014 19:22:10 +0100 Message-Id: <1395771730-16882-8-git-send-email-b.galvani@gmail.com> In-Reply-To: <1395771730-16882-1-git-send-email-b.galvani@gmail.com> References: <1395771730-16882-1-git-send-email-b.galvani@gmail.com> Subject: [Qemu-devel] [PATCH v5 7/7] allwinner-emac: update irq status after writes to interrupt registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Beniamino Galvani , Peter Maydell , Peter Crosthwaite , Li Guang The irq line status must be updated after writes to the INT_CTL and INT_STA registers. Signed-off-by: Beniamino Galvani Reviewed-by: Peter Crosthwaite --- hw/net/allwinner_emac.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/net/allwinner_emac.c b/hw/net/allwinner_emac.c index 91931ac..d780ba0 100644 --- a/hw/net/allwinner_emac.c +++ b/hw/net/allwinner_emac.c @@ -391,9 +391,11 @@ static void aw_emac_write(void *opaque, hwaddr offset, uint64_t value, break; case EMAC_INT_CTL_REG: s->int_ctl = value; + aw_emac_update_irq(s); break; case EMAC_INT_STA_REG: s->int_sta &= ~value; + aw_emac_update_irq(s); break; case EMAC_MAC_MADR_REG: s->phy_target = value; -- 1.7.10.4