From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33877) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WSuiN-0007Bc-8w for qemu-devel@nongnu.org; Wed, 26 Mar 2014 16:46:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WSuiE-0006Ek-Sg for qemu-devel@nongnu.org; Wed, 26 Mar 2014 16:46:23 -0400 From: Tom Musta Date: Wed, 26 Mar 2014 15:45:49 -0500 Message-Id: <1395866754-18673-5-git-send-email-tommusta@gmail.com> In-Reply-To: <1395866754-18673-1-git-send-email-tommusta@gmail.com> References: <1395866754-18673-1-git-send-email-tommusta@gmail.com> Subject: [Qemu-devel] [PATCH 4/9] target-ppc: Correct LE Host Inversion of Lower VSRs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Tom Musta , qemu-ppc@nongnu.org This change properly orders the doublewords of the VSRs 0-31. Because these registers are constructed from separate doublewords, they must be inverted on Little Endian hosts. The inversion is performed both when the VSR is read and when it is written. Signed-off-by: Tom Musta Tested-by: Tom Musta --- target-ppc/fpu_helper.c | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c index d79aae9..9fc7dd8 100644 --- a/target-ppc/fpu_helper.c +++ b/target-ppc/fpu_helper.c @@ -1793,8 +1793,8 @@ typedef union _ppc_vsr_t { static void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) { if (n < 32) { - vsr->f64[0] = env->fpr[n]; - vsr->u64[1] = env->vsr[n]; + vsr->VsrD(0) = env->fpr[n]; + vsr->VsrD(1) = env->vsr[n]; } else { vsr->u64[0] = env->avr[n-32].u64[0]; vsr->u64[1] = env->avr[n-32].u64[1]; @@ -1804,8 +1804,8 @@ static void getVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) static void putVSR(int n, ppc_vsr_t *vsr, CPUPPCState *env) { if (n < 32) { - env->fpr[n] = vsr->f64[0]; - env->vsr[n] = vsr->u64[1]; + env->fpr[n] = vsr->VsrD(0); + env->vsr[n] = vsr->VsrD(1); } else { env->avr[n-32].u64[0] = vsr->u64[0]; env->avr[n-32].u64[1] = vsr->u64[1]; -- 1.7.1