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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Cc: "Peter Crosthwaite" <peter.crosthwaite@xilinx.com>,
	patches@linaro.org, "Michael Matz" <matz@suse.de>,
	"Alexander Graf" <agraf@suse.de>,
	"Will Newton" <will.newton@linaro.org>,
	"Dirk Mueller" <dmueller@suse.de>,
	"Laurent Desnogues" <laurent.desnogues@gmail.com>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	kvmarm@lists.cs.columbia.edu,
	"Christoffer Dall" <christoffer.dall@linaro.org>,
	"Richard Henderson" <rth@twiddle.net>
Subject: [Qemu-devel] [PATCH v5 00/37] AArch64 system emulation
Date: Fri, 28 Mar 2014 16:09:47 +0000	[thread overview]
Message-ID: <1396023024-2262-1-git-send-email-peter.maydell@linaro.org> (raw)

Here's v5 of the AArch64 system emulation patchset.
Still missing/TODO:
 * haven't dealt with the use of a15mpcore_priv in the virt
   machine patch yet; Peter C's suggestion in review on v4 is
   probably the right thing, I just haven't got to it yet
 * SMP support (needs PSCI emulation in QEMU; being prototyped)
 * save/restore (I have a patch which adds this but I think it will
   look better if we consolidate AArch32 cpsr and AArch64 pstate
   handling)

Changes v4->v5:
 * new patches:
   + MVFR registers
   + various extra system registers
   + don't expose wildcards for ARMv8
   + make A15's CBAR R/O
   + support interprocessing in set_pc
 * minor tweaks per review (I haven't always taken the review
   suggestion; see mail threads on the previous version of the
   patch series)
 * DC ZVA: use helper_ret_stb_mmu
           make tlb_vaddr_to_host take param for access type
 * NB: I didn't make gen_exception and gen_exception_internal shared
   in patch 5: I think keeping the A64 and A32 decoders independent
   is preferable
 * have syn_insn_abort and syn_data_abort set the syndrome bit
   for 'exception to same level' rather than making caller do it
Changes v3->v4:
 * reviewed patches from bottom of stack got committed to master
 * new patches at top of stack
 * addressed review issues on v8 mmu translation patch and DAIF patch

thanks
-- PMM

Peter Maydell (33):
  target-arm: Split out private-to-target functions into internals.h
  target-arm: Implement AArch64 DAIF system register
  target-arm: Define exception record for AArch64 exceptions
  target-arm: Provide correct syndrome information for cpreg access
    traps
  target-arm: Add support for generating exceptions with syndrome
    information
  target-arm: A64: Correctly fault FP/Neon if CPACR.FPEN set
  target-arm: A64: Add assertion that FP access was checked
  target-arm: Fix VFP enables for AArch32 EL0 under AArch64 EL1
  target-arm: Don't mention PMU in debug feature register
  target-arm: A64: Implement DC ZVA
  target-arm: Use dedicated CPU state fields for ARM946 access bit
    registers
  target-arm: Add AArch64 ELR_EL1 register.
  target-arm: Implement SP_EL0, SP_EL1
  target-arm: Implement AArch64 SPSR_EL1
  target-arm: Move arm_log_exception() into internals.h
  target-arm: Implement ARMv8 MVFR registers
  target-arm: Add Cortex-A57 processor
  hw/arm/virt: Add support for Cortex-A57
  target-arm: Implement AArch64 views of AArch32 ID registers
  target-arm: Implement AArch64 view of CONTEXTIDR
  target-arm: Implement AArch64 view of ACTLR
  target-arm: Implement ISR_EL1 register
  target-arm: Remove THUMB2EE feature from AArch64 'any' CPU
  target-arm: Don't expose wildcard ID register definitions for ARMv8
  target-arm: Replace wildcarded cpreg definitions with precise ones for
    ARMv8
  target-arm: Implement auxiliary fault status registers
  target-arm: Implement AArch64 address translation operations
  target-arm: Implement RVBAR register
  target-arm: Implement Cortex-A57 implementation-defined system
    registers
  target-arm: Implement CBAR for Cortex-A57
  target-arm: Make Cortex-A15 CBAR read-only
  target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pc
  target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32

Rob Herring (4):
  target-arm: Provide syndrome information for MMU faults
  target-arm: Add v8 mmu translation support
  target-arm: Implement AArch64 views of fault status and data registers
  target-arm: Implement AArch64 EL1 exception handling

 hw/arm/virt.c               |   8 +
 include/exec/softmmu_exec.h |  52 +++
 linux-user/main.c           |  56 ++-
 target-arm/cpu-qom.h        |  10 +-
 target-arm/cpu.c            |  30 +-
 target-arm/cpu.h            |  81 +++--
 target-arm/cpu64.c          | 115 ++++++-
 target-arm/helper-a64.c     |  75 ++++
 target-arm/helper.c         | 809 +++++++++++++++++++++++++++++++++-----------
 target-arm/helper.h         |   7 +-
 target-arm/internals.h      | 267 +++++++++++++++
 target-arm/kvm32.c          |  19 +-
 target-arm/kvm64.c          |  71 +++-
 target-arm/machine.c        |  13 +-
 target-arm/op_helper.c      |  92 ++++-
 target-arm/translate-a64.c  | 440 +++++++++++++++++++++---
 target-arm/translate.c      | 183 +++++++---
 target-arm/translate.h      |  23 +-
 18 files changed, 1974 insertions(+), 377 deletions(-)
 create mode 100644 target-arm/internals.h

-- 
1.9.0

             reply	other threads:[~2014-03-28 16:27 UTC|newest]

Thread overview: 53+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-03-28 16:09 Peter Maydell [this message]
2014-03-28 16:09 ` [Qemu-devel] [PATCH v5 01/37] target-arm: Split out private-to-target functions into internals.h Peter Maydell
2014-03-28 16:09 ` [Qemu-devel] [PATCH v5 02/37] target-arm: Implement AArch64 DAIF system register Peter Maydell
2014-03-28 16:09 ` [Qemu-devel] [PATCH v5 03/37] target-arm: Define exception record for AArch64 exceptions Peter Maydell
2014-03-28 16:09 ` [Qemu-devel] [PATCH v5 04/37] target-arm: Provide correct syndrome information for cpreg access traps Peter Maydell
2014-03-28 16:09 ` [Qemu-devel] [PATCH v5 05/37] target-arm: Add support for generating exceptions with syndrome information Peter Maydell
2014-03-28 16:09 ` [Qemu-devel] [PATCH v5 06/37] target-arm: Provide syndrome information for MMU faults Peter Maydell
2014-04-01  3:10   ` Peter Crosthwaite
2014-04-04 13:25     ` Peter Maydell
2014-03-28 16:09 ` [Qemu-devel] [PATCH v5 07/37] target-arm: A64: Correctly fault FP/Neon if CPACR.FPEN set Peter Maydell
2014-03-28 16:09 ` [Qemu-devel] [PATCH v5 08/37] target-arm: A64: Add assertion that FP access was checked Peter Maydell
2014-04-01  3:24   ` Peter Crosthwaite
2014-03-28 16:09 ` [Qemu-devel] [PATCH v5 09/37] target-arm: Fix VFP enables for AArch32 EL0 under AArch64 EL1 Peter Maydell
2014-04-01  3:30   ` Peter Crosthwaite
2014-03-28 16:09 ` [Qemu-devel] [PATCH v5 10/37] target-arm: Add v8 mmu translation support Peter Maydell
2014-03-28 16:09 ` [Qemu-devel] [PATCH v5 11/37] target-arm: Don't mention PMU in debug feature register Peter Maydell
2014-04-01 13:19   ` Christopher Covington
2014-04-01 13:43     ` Peter Maydell
2014-03-28 16:09 ` [Qemu-devel] [PATCH v5 12/37] target-arm: A64: Implement DC ZVA Peter Maydell
2014-03-28 18:42   ` Richard Henderson
2014-04-04 14:12     ` Peter Maydell
2014-03-28 16:10 ` [Qemu-devel] [PATCH v5 13/37] target-arm: Use dedicated CPU state fields for ARM946 access bit registers Peter Maydell
2014-03-28 16:10 ` [Qemu-devel] [PATCH v5 14/37] target-arm: Implement AArch64 views of fault status and data registers Peter Maydell
2014-03-28 16:10 ` [Qemu-devel] [PATCH v5 15/37] target-arm: Add AArch64 ELR_EL1 register Peter Maydell
2014-03-28 16:10 ` [Qemu-devel] [PATCH v5 16/37] target-arm: Implement SP_EL0, SP_EL1 Peter Maydell
2014-03-28 16:10 ` [Qemu-devel] [PATCH v5 17/37] target-arm: Implement AArch64 SPSR_EL1 Peter Maydell
2014-03-28 16:10 ` [Qemu-devel] [PATCH v5 18/37] target-arm: Move arm_log_exception() into internals.h Peter Maydell
2014-03-28 16:10 ` [Qemu-devel] [PATCH v5 19/37] target-arm: Implement AArch64 EL1 exception handling Peter Maydell
2014-03-28 16:10 ` [Qemu-devel] [PATCH v5 20/37] target-arm: Implement ARMv8 MVFR registers Peter Maydell
2014-03-28 16:10 ` [Qemu-devel] [PATCH v5 21/37] target-arm: Add Cortex-A57 processor Peter Maydell
2014-03-28 16:10 ` [Qemu-devel] [PATCH v5 22/37] hw/arm/virt: Add support for Cortex-A57 Peter Maydell
2014-03-28 16:10 ` [Qemu-devel] [PATCH v5 23/37] target-arm: Implement AArch64 views of AArch32 ID registers Peter Maydell
2014-03-28 16:10 ` [Qemu-devel] [PATCH v5 24/37] target-arm: Implement AArch64 view of CONTEXTIDR Peter Maydell
2014-03-28 16:10 ` [Qemu-devel] [PATCH v5 25/37] target-arm: Implement AArch64 view of ACTLR Peter Maydell
2014-03-28 16:10 ` [Qemu-devel] [PATCH v5 26/37] target-arm: Implement ISR_EL1 register Peter Maydell
2014-03-28 16:10 ` [Qemu-devel] [PATCH v5 27/37] target-arm: Remove THUMB2EE feature from AArch64 'any' CPU Peter Maydell
2014-04-02 12:20   ` Peter Crosthwaite
2014-03-28 16:10 ` [Qemu-devel] [PATCH v5 28/37] target-arm: Don't expose wildcard ID register definitions for ARMv8 Peter Maydell
2014-03-28 16:10 ` [Qemu-devel] [PATCH v5 29/37] target-arm: Replace wildcarded cpreg definitions with precise ones " Peter Maydell
2014-03-28 16:10 ` [Qemu-devel] [PATCH v5 30/37] target-arm: Implement auxiliary fault status registers Peter Maydell
2014-03-28 16:10 ` [Qemu-devel] [PATCH v5 31/37] target-arm: Implement AArch64 address translation operations Peter Maydell
2014-03-28 16:10 ` [Qemu-devel] [PATCH v5 32/37] target-arm: Implement RVBAR register Peter Maydell
2014-04-04  5:17   ` Peter Crosthwaite
2014-03-28 16:10 ` [Qemu-devel] [PATCH v5 33/37] target-arm: Implement Cortex-A57 implementation-defined system registers Peter Maydell
2014-03-28 16:10 ` [Qemu-devel] [PATCH v5 34/37] target-arm: Implement CBAR for Cortex-A57 Peter Maydell
2014-04-04  5:32   ` Peter Crosthwaite
2014-04-04  8:25     ` Peter Maydell
2014-04-04 12:32       ` Peter Crosthwaite
2014-04-04 13:05         ` Peter Maydell
2014-03-28 16:10 ` [Qemu-devel] [PATCH v5 35/37] target-arm: Make Cortex-A15 CBAR read-only Peter Maydell
2014-04-04  5:33   ` Peter Crosthwaite
2014-03-28 16:10 ` [Qemu-devel] [PATCH v5 36/37] target-arm: Handle the CPU being in AArch32 mode in the AArch64 set_pc Peter Maydell
2014-03-28 16:10 ` [Qemu-devel] [PATCH v5 37/37] target-arm: Dump 32-bit CPU state if 64 bit CPU is in AArch32 Peter Maydell

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