From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58985) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WXA1V-0002dG-D1 for qemu-devel@nongnu.org; Mon, 07 Apr 2014 09:55:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WXA1M-0001Nd-B1 for qemu-devel@nongnu.org; Mon, 07 Apr 2014 09:55:41 -0400 Received: from mail-wi0-x22e.google.com ([2a00:1450:400c:c05::22e]:62326) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WXA1L-0001N4-V9 for qemu-devel@nongnu.org; Mon, 07 Apr 2014 09:55:32 -0400 Received: by mail-wi0-f174.google.com with SMTP id d1so5124461wiv.1 for ; Mon, 07 Apr 2014 06:55:30 -0700 (PDT) Message-ID: <1396878953.10570.21.camel@localhost.localdomain> From: Marcel Apfelbaum Date: Mon, 07 Apr 2014 16:55:53 +0300 In-Reply-To: <1396878714.10570.18.camel@localhost.localdomain> References: <1396868342-12005-1-git-send-email-marcel.a@redhat.com> <20140407121508.GD16369@redhat.com> <1396874646.5001.76.camel@nilsson.home.kraxel.org> <20140407133415.GB16541@redhat.com> <1396878714.10570.18.camel@localhost.localdomain> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [SeaBIOS] [PATCH] hw/pci: reserve IO and mem for pci-2-pci bridges with no devices attached Reply-To: marcel.a@redhat.com List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" Cc: seabios@seabios.org, Gerd Hoffmann , qemu-devel@nongnu.org On Mon, 2014-04-07 at 16:51 +0300, Marcel Apfelbaum wrote: > On Mon, 2014-04-07 at 16:34 +0300, Michael S. Tsirkin wrote: > > On Mon, Apr 07, 2014 at 02:44:06PM +0200, Gerd Hoffmann wrote: > > > Hi, > > > > > > > > + u8 shpc_cap = pci_find_capability(s->bus_dev, PCI_CAP_ID_SHPC); > > > > > > > One thing I'd do is maybe check that the relevant memory type is > > > > enabled in the bridge (probably just by writing fff to base and reading > > > > it back). > > > > > > > This will give hypervisors an option to avoid wasting resources: > > > > e.g. it's uncommon for express devices to claim IO. > > > > > > I don't think we'll need that for the SHPC bridge. > > > > Why not? > Because "has shpc" => not an PCIe port. (as far as I know) > Anyway, why have shpc capability but no I/O or mem to support it? > I signed too soon :), I have another question below, > Thanks, > Marcel > [...] > > > > So we should probe bridge for I/O support before wasting I/O resources on it. > > The spec does not provide a way to detect this, but we can do it like this: > > > > - write value ffffffff to I/O base register > Why write? A simple read would be enough. > It will never be 0(if I/O or mem is required) because of the "Base Address" > part of the register which represents the address range, right? Here ^^^ > > Thanks, > Marcel [...]