From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48155) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WXSO0-0001OB-Tm for qemu-devel@nongnu.org; Tue, 08 Apr 2014 05:32:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WXSNp-0004t3-4U for qemu-devel@nongnu.org; Tue, 08 Apr 2014 05:32:08 -0400 From: Alexander Graf Date: Tue, 8 Apr 2014 11:31:40 +0200 Message-Id: <1396949514-10494-2-git-send-email-agraf@suse.de> In-Reply-To: <1396949514-10494-1-git-send-email-agraf@suse.de> References: <1396949514-10494-1-git-send-email-agraf@suse.de> Subject: [Qemu-devel] [PULL 2.0 01/15] PPC: E500: Set PIR default reset value rather than SPR value List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, qemu-ppc@nongnu.org We now reset SPRs to their reset values on CPU reset. So if we want to have an SPR persistently changed, we need to change its default reset value rather than the value itself manually. Do this for SPR_BOOKE_PIR, fixing e500v2 SMP boot. Reported-by: Frederic Konrad Signed-off-by: Alexander Graf Tested-by: KONRAD Frederic --- hw/ppc/e500.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index d7ba25f..f984b3e 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -649,7 +649,7 @@ void ppce500_init(QEMUMachineInitArgs *args, PPCE500Params *params) input = (qemu_irq *)env->irq_inputs; irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT]; irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT]; - env->spr[SPR_BOOKE_PIR] = cs->cpu_index = i; + env->spr_cb[SPR_BOOKE_PIR].default_value = cs->cpu_index = i; env->mpic_iack = MPC8544_CCSRBAR_BASE + MPC8544_MPIC_REGS_OFFSET + 0xa0; -- 1.8.1.4