From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40534) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WYHdw-0003qk-IA for qemu-devel@nongnu.org; Thu, 10 Apr 2014 12:16:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WYHdv-0003Vr-Bm for qemu-devel@nongnu.org; Thu, 10 Apr 2014 12:16:00 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:47599) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WYHdv-0003O1-5T for qemu-devel@nongnu.org; Thu, 10 Apr 2014 12:15:59 -0400 From: Peter Maydell Date: Thu, 10 Apr 2014 17:15:29 +0100 Message-Id: <1397146536-30116-31-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1397146536-30116-1-git-send-email-peter.maydell@linaro.org> References: <1397146536-30116-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PATCH v6 30/37] target-arm: Implement auxiliary fault status registers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Crosthwaite , patches@linaro.org, Alexander Graf , Greg Bellows , Laurent Desnogues , =?UTF-8?q?Alex=20Benn=C3=A9e?= , kvmarm@lists.cs.columbia.edu, Christoffer Dall , Richard Henderson Implement the auxiliary fault status registers AFSR0_EL1 and AFSR1_EL1. These are present on v7 and later, and have IMPDEF behaviour; we choose to RAZ/WI for all cores. Signed-off-by: Peter Maydell --- target-arm/helper.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 1d1e7b4..988a8e9 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -784,6 +784,15 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { { .name = "AIDR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, + /* Auxiliary fault status registers: these also are IMPDEF, and we + * choose to RAZ/WI for all cores. + */ + { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0, + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, + { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1, + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, /* MAIR can just read-as-written because we don't implement caches * and so don't need to care about memory attributes. */ -- 1.9.1