From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46301) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WfscD-0001tc-3g for qemu-devel@nongnu.org; Thu, 01 May 2014 11:09:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WfscA-0000SG-GQ for qemu-devel@nongnu.org; Thu, 01 May 2014 11:09:36 -0400 Received: from mnementh.archaic.org.uk ([2001:8b0:1d0::1]:47976) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WfscA-0000Ry-8v for qemu-devel@nongnu.org; Thu, 01 May 2014 11:09:34 -0400 From: Peter Maydell Date: Thu, 1 May 2014 15:54:58 +0100 Message-Id: <1398956107-7411-2-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1398956107-7411-1-git-send-email-peter.maydell@linaro.org> References: <1398956107-7411-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 01/10] target-arm: Implement XScale cache lockdown operations as NOPs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori Cc: qemu-devel@nongnu.org XScale defines some implementation-specific coprocessor registers for doing cache lockdown operations. Since QEMU doesn't model a cache no proper implementation is possible, but NOP out the registers so that guest code like u-boot that tries to use them doesn't crash. Reported-by: Signed-off-by: Peter Maydell --- target-arm/helper.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 43c1b4f..7c083c3 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1578,6 +1578,21 @@ static const ARMCPRegInfo xscale_cp_reginfo[] = { .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr), .resetvalue = 0, }, + /* XScale specific cache-lockdown: since we have no cache we NOP these + * and hope the guest does not really rely on cache behaviour. + */ + { .name = "XSCALE_LOCK_ICACHE_LINE", + .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, + .access = PL1_W, .type = ARM_CP_NOP }, + { .name = "XSCALE_UNLOCK_ICACHE", + .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, + .access = PL1_W, .type = ARM_CP_NOP }, + { .name = "XSCALE_DCACHE_LOCK", + .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0, + .access = PL1_RW, .type = ARM_CP_NOP }, + { .name = "XSCALE_UNLOCK_DCACHE", + .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1, + .access = PL1_W, .type = ARM_CP_NOP }, REGINFO_SENTINEL }; -- 1.9.2