From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60004) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WftBF-0004rE-1k for qemu-devel@nongnu.org; Thu, 01 May 2014 11:45:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WftB9-0006sN-13 for qemu-devel@nongnu.org; Thu, 01 May 2014 11:45:48 -0400 Received: from mail-qg0-x22f.google.com ([2607:f8b0:400d:c04::22f]:53185) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WftB8-0006s9-K7 for qemu-devel@nongnu.org; Thu, 01 May 2014 11:45:42 -0400 Received: by mail-qg0-f47.google.com with SMTP id e89so3431129qgf.20 for ; Thu, 01 May 2014 08:45:42 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Thu, 1 May 2014 08:44:34 -0700 Message-Id: <1398959087-23590-14-git-send-email-rth@twiddle.net> In-Reply-To: <1398959087-23590-1-git-send-email-rth@twiddle.net> References: <1398959087-23590-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 13/26] tcg-ppc64: Merge 32-bit ABIs into the prologue / frame code List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: av1474@comtv.ru Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 39 ++++++++++++++++++++++++++++++++------- 1 file changed, 32 insertions(+), 7 deletions(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index 635ff98..8d932eb 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -24,6 +24,10 @@ #include "tcg-be-ldst.h" +#if defined _CALL_DARWIN || defined __APPLE__ +#define TCG_TARGET_CALL_DARWIN +#endif + /* Shorthand for size of a pointer. Avoid promotion to unsigned. */ #define SZP ((int)sizeof(void *)) @@ -1431,12 +1435,26 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, # define LINK_AREA_SIZE (6 * SZR) # define LR_OFFSET (1 * SZR) # define TCG_TARGET_CALL_STACK_OFFSET (LINK_AREA_SIZE + 8 * SZR) -#elif defined(_CALL_ELF) && _CALL_ELF == 2 -# define LINK_AREA_SIZE (4 * SZR) -# define LR_OFFSET (1 * SZR) +#elif TCG_TARGET_REG_BITS == 64 +# if defined(_CALL_ELF) && _CALL_ELF == 2 +# define LINK_AREA_SIZE (4 * SZR) +# define LR_OFFSET (1 * SZR) +# endif +#else /* TCG_TARGET_REG_BITS == 32 */ +# if defined(_CALL_SYSV) +# define TCG_TARGET_CALL_ALIGN_ARGS 1 +# define LINK_AREA_SIZE (2 * SZR) +# define LR_OFFSET (1 * SZR) +# elif defined(TCG_TARGET_CALL_DARWIN) +# define LINK_AREA_SIZE 24 +# define LR_OFFSET 8 +# endif +#endif +#ifndef LR_OFFSET +# error "Unhandled abi" +#endif +#ifndef TCG_TARGET_CALL_STACK_OFFSET # define TCG_TARGET_CALL_STACK_OFFSET LINK_AREA_SIZE -#else -# error #endif #define CPU_TEMP_BUF_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) @@ -1469,7 +1487,8 @@ static void tcg_target_qemu_prologue(TCGContext *s) /* Prologue */ tcg_out32(s, MFSPR | RT(TCG_REG_R0) | LR); - tcg_out32(s, STDU | SAI(TCG_REG_R1, TCG_REG_R1, -FRAME_SIZE)); + tcg_out32(s, (SZR == 8 ? STDU : STWU) + | SAI(TCG_REG_R1, TCG_REG_R1, -FRAME_SIZE)); for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) { tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], @@ -2169,6 +2188,7 @@ static void tcg_target_init(TCGContext *s) tcg_add_target_add_op_defs(ppc_op_defs); } +#ifdef __ELF__ typedef struct { DebugFrameCIE cie; DebugFrameFDEHeader fde; @@ -2179,7 +2199,11 @@ typedef struct { /* We're expecting a 2 byte uleb128 encoded value. */ QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); -#define ELF_HOST_MACHINE EM_PPC64 +#if TCG_TARGET_REG_BITS == 64 +# define ELF_HOST_MACHINE EM_PPC64 +#else +# define ELF_HOST_MACHINE EM_PPC +#endif static DebugFrame debug_frame = { .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ @@ -2218,3 +2242,4 @@ void tcg_register_jit(void *buf, size_t buf_size) tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); } +#endif /* __ELF__ */ -- 1.9.0