From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60079) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WftBN-00056b-De for qemu-devel@nongnu.org; Thu, 01 May 2014 11:46:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WftBH-0006uE-5E for qemu-devel@nongnu.org; Thu, 01 May 2014 11:45:57 -0400 Received: from mail-qg0-x229.google.com ([2607:f8b0:400d:c04::229]:33344) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WftBH-0006tw-1s for qemu-devel@nongnu.org; Thu, 01 May 2014 11:45:51 -0400 Received: by mail-qg0-f41.google.com with SMTP id j107so3471798qga.28 for ; Thu, 01 May 2014 08:45:50 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Thu, 1 May 2014 08:44:40 -0700 Message-Id: <1398959087-23590-20-git-send-email-rth@twiddle.net> In-Reply-To: <1398959087-23590-1-git-send-email-rth@twiddle.net> References: <1398959087-23590-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 19/26] tcg-ppc64: Support mulsh_i32 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: av1474@comtv.ru Signed-off-by: Richard Henderson --- tcg/ppc64/tcg-target.c | 5 +++++ tcg/ppc64/tcg-target.h | 2 +- 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index cd68834..860c408 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -410,6 +410,7 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type, #define OR XO31(444) #define XOR XO31(316) #define MULLW XO31(235) +#define MULHW XO31( 75) #define MULHWU XO31( 11) #define DIVW XO31(491) #define DIVWU XO31(459) @@ -2260,6 +2261,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, case INDEX_op_muluh_i32: tcg_out32(s, MULHWU | TAB(args[0], args[1], args[2])); break; + case INDEX_op_mulsh_i32: + tcg_out32(s, MULHW | TAB(args[1], args[2], args[3])); + break; case INDEX_op_muluh_i64: tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2])); break; @@ -2326,6 +2330,7 @@ static const TCGTargetOpDef ppc_op_defs[] = { { INDEX_op_deposit_i32, { "r", "0", "rZ" } }, { INDEX_op_muluh_i32, { "r", "r", "r" } }, + { INDEX_op_mulsh_i32, { "r", "r", "r" } }, #if TCG_TARGET_REG_BITS == 64 { INDEX_op_ld8u_i64, { "r", "r" } }, diff --git a/tcg/ppc64/tcg-target.h b/tcg/ppc64/tcg-target.h index 6b1dffd..5ba7a2e 100644 --- a/tcg/ppc64/tcg-target.h +++ b/tcg/ppc64/tcg-target.h @@ -71,7 +71,7 @@ typedef enum { #define TCG_TARGET_HAS_mulu2_i32 0 #define TCG_TARGET_HAS_muls2_i32 0 #define TCG_TARGET_HAS_muluh_i32 1 -#define TCG_TARGET_HAS_mulsh_i32 0 +#define TCG_TARGET_HAS_mulsh_i32 1 #if TCG_TARGET_REG_BITS == 64 #define TCG_TARGET_HAS_add2_i32 0 -- 1.9.0