From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: av1474@comtv.ru
Subject: [Qemu-devel] [PATCH 02/26] tcg-ppc64: Avoid some hard-codings of TCG_TYPE_I64
Date: Thu, 1 May 2014 08:44:23 -0700 [thread overview]
Message-ID: <1398959087-23590-3-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1398959087-23590-1-git-send-email-rth@twiddle.net>
Using more appropriate _PTR or _REG where possible.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/ppc64/tcg-target.c | 23 +++++++++++++----------
1 file changed, 13 insertions(+), 10 deletions(-)
diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index c90ddcd..2f60924 100644
--- a/tcg/ppc64/tcg-target.c
+++ b/tcg/ppc64/tcg-target.c
@@ -24,6 +24,9 @@
#include "tcg-be-ldst.h"
+/* Shorthand for size of a pointer. Avoid promotion to unsigned. */
+#define SZP ((int)sizeof(void *))
+
#define TCG_CT_CONST_S16 0x100
#define TCG_CT_CONST_U16 0x200
#define TCG_CT_CONST_S32 0x400
@@ -701,7 +704,7 @@ static void tcg_out_b(TCGContext *s, int mask, tcg_insn_unit *target)
if (in_range_b(disp)) {
tcg_out32(s, B | (disp & 0x3fffffc) | mask);
} else {
- tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, (uintptr_t)target);
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, (uintptr_t)target);
tcg_out32(s, MTSPR | RS(TCG_REG_R0) | CTR);
tcg_out32(s, BCCTR | BO_ALWAYS | mask);
}
@@ -719,7 +722,7 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit *target)
intptr_t diff = tcg_pcrel_diff(s, tgt);
if (in_range_b(diff) && toc == (uint32_t)toc) {
- tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R2, toc);
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, toc);
tcg_out_b(s, LK, tgt);
} else {
/* Fold the low bits of the constant into the addresses below. */
@@ -731,7 +734,7 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit *target)
} else {
ofs = 0;
}
- tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R2, arg);
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg);
tcg_out32(s, LD | TAI(TCG_REG_R0, TCG_REG_R2, ofs));
tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR);
tcg_out32(s, LD | TAI(TCG_REG_R2, TCG_REG_R2, ofs + 8));
@@ -766,7 +769,7 @@ static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
/* For unaligned, or very large offsets, use the indexed form. */
if (offset & align || offset != (int32_t)offset) {
- tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R2, orig);
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, orig);
tcg_out32(s, opx | TAB(rt, base, TCG_REG_R2));
return;
}
@@ -1118,7 +1121,7 @@ static void tcg_target_qemu_prologue(TCGContext *s)
#ifdef CONFIG_USE_GUEST_BASE
if (GUEST_BASE) {
- tcg_out_movi(s, TCG_TYPE_I64, TCG_GUEST_BASE_REG, GUEST_BASE);
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, GUEST_BASE);
tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
}
#endif
@@ -1476,7 +1479,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
switch (opc) {
case INDEX_op_exit_tb:
- tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R3, args[0]);
+ tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]);
tcg_out_b(s, 0, tb_ret_addr);
break;
case INDEX_op_goto_tb:
@@ -1868,7 +1871,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
if (a0 == TCG_REG_R0) {
- tcg_out_mov(s, TCG_TYPE_I64, args[0], a0);
+ tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
}
break;
@@ -1900,7 +1903,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
tcg_out_rlw(s, RLWIMI, a0, a2, 24, 16, 23);
if (a0 == 0) {
- tcg_out_mov(s, TCG_TYPE_I64, args[0], a0);
+ tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
}
break;
@@ -1951,7 +1954,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
tcg_out32(s, ADDE | TAB(a1, args[3], args[5]));
}
if (a0 != args[0]) {
- tcg_out_mov(s, TCG_TYPE_I64, args[0], a0);
+ tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
}
break;
@@ -1971,7 +1974,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
tcg_out32(s, SUBFE | TAB(a1, args[5], args[4]));
}
if (a0 != args[0]) {
- tcg_out_mov(s, TCG_TYPE_I64, args[0], a0);
+ tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
}
break;
--
1.9.0
next prev parent reply other threads:[~2014-05-01 15:45 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-01 15:44 [Qemu-devel] [PATCH 00/26] Merge ppc32/ppc64 tcg backends Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 01/26] tcg-ppc: Use uintptr_t in ppc_tb_set_jmp_target Richard Henderson
2014-05-01 15:44 ` Richard Henderson [this message]
2014-05-01 15:44 ` [Qemu-devel] [PATCH 03/26] tcg-ppc64: Move functions around Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 04/26] tcg-ppc64: Relax register restrictions in tcg_out_mem_long Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 05/26] tcg-ppc64: Use tcg_out_{ld, st, cmp} internally Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 06/26] tcg-ppc64: Make TCG_AREG0 and TCG_REG_CALL_STACK enum constants Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 07/26] tcg-ppc64: Move call macros out of tcg-target.h Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 08/26] tcg-ppc64: Fix TCG_TARGET_CALL_STACK_OFFSET Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 09/26] tcg-ppc64: Better parameterize the stack frame Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 10/26] tcg-ppc64: Use the correct test in tcg_out_call Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 11/26] tcg-ppc64: Support the ppc64 elfv2 ABI Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 12/26] tcg-ppc64: Adjust tcg_out_call for ELFv2 Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 13/26] tcg-ppc64: Merge 32-bit ABIs into the prologue / frame code Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 14/26] tcg-ppc64: Fix sub2 implementation Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 15/26] tcg-ppc64: Begin merging ppc32 with ppc64 Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 16/26] tcg-ppc64: Merge ppc32 brcond2, setcond2, muluh Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 17/26] tcg-ppc64: Merge ppc32 qemu_ld/st Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 18/26] tcg-ppc64: Merge ppc32 register usage Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 19/26] tcg-ppc64: Support mulsh_i32 Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 20/26] tcg-ppc64: Merge ppc32 shifts Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 21/26] tcg-ppc: Remove the backend Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 22/26] tcg-ppc: Rename the tcg/ppc64 backend Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 23/26] qemu/osdep: Remove the need for qemu_init_auxval Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 24/26] tcg-ppc: Merge cache-utils into the backend Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 25/26] tcg-ppc64: Use the return address as a base pointer Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 26/26] tcg-ppc: Streamline USE_DIRECT_JUMP Richard Henderson
2014-05-02 14:56 ` [Qemu-devel] [PATCH 00/26] Merge ppc32/ppc64 tcg backends Tom Musta
2014-05-02 16:30 ` Ulrich Weigand
2014-05-02 16:43 ` Richard Henderson
2014-05-05 20:32 ` Tom Musta
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