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From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: av1474@comtv.ru
Subject: [Qemu-devel] [PATCH 05/26] tcg-ppc64: Use tcg_out_{ld, st, cmp} internally
Date: Thu,  1 May 2014 08:44:26 -0700	[thread overview]
Message-ID: <1398959087-23590-6-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1398959087-23590-1-git-send-email-rth@twiddle.net>

Rather than using tcg_out32 and opcodes directly.  This allows us
to remove LD_ADDR and CMP_L macros.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/ppc64/tcg-target.c | 33 ++++++++++++++-------------------
 1 file changed, 14 insertions(+), 19 deletions(-)

diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c
index dbe9c5c..17f422e 100644
--- a/tcg/ppc64/tcg-target.c
+++ b/tcg/ppc64/tcg-target.c
@@ -27,6 +27,9 @@
 /* Shorthand for size of a pointer.  Avoid promotion to unsigned.  */
 #define SZP  ((int)sizeof(void *))
 
+/* Shorthand for size of a register.  */
+#define SZR  (TCG_TARGET_REG_BITS / 8)
+
 #define TCG_CT_CONST_S16  0x100
 #define TCG_CT_CONST_U16  0x200
 #define TCG_CT_CONST_S32  0x400
@@ -36,14 +39,6 @@
 
 static tcg_insn_unit *tb_ret_addr;
 
-#if TARGET_LONG_BITS == 32
-#define LD_ADDR LWZ
-#define CMP_L 0
-#else
-#define LD_ADDR LD
-#define CMP_L (1<<21)
-#endif
-
 #ifndef GUEST_BASE
 #define GUEST_BASE 0
 #endif
@@ -1117,9 +1112,9 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit *target)
             ofs = 0;
         }
         tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg);
-        tcg_out32(s, LD | TAI(TCG_REG_R0, TCG_REG_R2, ofs));
+        tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R2, ofs);
         tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR);
-        tcg_out32(s, LD | TAI(TCG_REG_R2, TCG_REG_R2, ofs + 8));
+        tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_REG_R2, ofs + SZP);
         tcg_out32(s, BCCTR | BO_ALWAYS | LK);
     }
 #endif
@@ -1231,11 +1226,11 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp s_bits, TCGReg addr_reg,
     tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, base));
 
     /* Load the tlb comparator.  */
-    tcg_out32(s, LD_ADDR | TAI(TCG_REG_R2, TCG_REG_R3, cmp_off));
+    tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_R2, TCG_REG_R3, cmp_off);
 
     /* Load the TLB addend for use on the fast path.  Do this asap
        to minimize any load use delay.  */
-    tcg_out32(s, LD | TAI(TCG_REG_R3, TCG_REG_R3, add_off));
+    tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_REG_R3, add_off);
 
     /* Clear the non-page, non-alignment bits from the address.  */
     if (TARGET_LONG_BITS == 32) {
@@ -1249,7 +1244,7 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp s_bits, TCGReg addr_reg,
         tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0);
     }
 
-    tcg_out32(s, CMP | BF(7) | RA(TCG_REG_R0) | RB(TCG_REG_R2) | CMP_L);
+    tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_R2, 0, 7, TCG_TYPE_TL);
 
     return addr_reg;
 }
@@ -1444,10 +1439,10 @@ static void tcg_target_qemu_prologue(TCGContext *s)
     tcg_out32(s, MFSPR | RT(TCG_REG_R0) | LR);
     tcg_out32(s, STDU | SAI(TCG_REG_R1, TCG_REG_R1, -FRAME_SIZE));
     for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
-        tcg_out32(s, STD | SAI(tcg_target_callee_save_regs[i], 1, 
-                               REG_SAVE_BOT + i * 8));
+        tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
+                   TCG_REG_R1, REG_SAVE_BOT + i * SZR);
     }
-    tcg_out32(s, STD | SAI(TCG_REG_R0, TCG_REG_R1, FRAME_SIZE + 16));
+    tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE + 16);
 
 #ifdef CONFIG_USE_GUEST_BASE
     if (GUEST_BASE) {
@@ -1464,10 +1459,10 @@ static void tcg_target_qemu_prologue(TCGContext *s)
     tb_ret_addr = s->code_ptr;
 
     for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
-        tcg_out32(s, LD | TAI(tcg_target_callee_save_regs[i], TCG_REG_R1,
-                              REG_SAVE_BOT + i * 8));
+        tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
+                   TCG_REG_R1, REG_SAVE_BOT + i * SZR);
     }
-    tcg_out32(s, LD | TAI(TCG_REG_R0, TCG_REG_R1, FRAME_SIZE + 16));
+    tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE + 16);
     tcg_out32(s, MTSPR | RS(TCG_REG_R0) | LR);
     tcg_out32(s, ADDI | TAI(TCG_REG_R1, TCG_REG_R1, FRAME_SIZE));
     tcg_out32(s, BCLR | BO_ALWAYS);
-- 
1.9.0

  parent reply	other threads:[~2014-05-01 15:45 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-05-01 15:44 [Qemu-devel] [PATCH 00/26] Merge ppc32/ppc64 tcg backends Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 01/26] tcg-ppc: Use uintptr_t in ppc_tb_set_jmp_target Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 02/26] tcg-ppc64: Avoid some hard-codings of TCG_TYPE_I64 Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 03/26] tcg-ppc64: Move functions around Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 04/26] tcg-ppc64: Relax register restrictions in tcg_out_mem_long Richard Henderson
2014-05-01 15:44 ` Richard Henderson [this message]
2014-05-01 15:44 ` [Qemu-devel] [PATCH 06/26] tcg-ppc64: Make TCG_AREG0 and TCG_REG_CALL_STACK enum constants Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 07/26] tcg-ppc64: Move call macros out of tcg-target.h Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 08/26] tcg-ppc64: Fix TCG_TARGET_CALL_STACK_OFFSET Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 09/26] tcg-ppc64: Better parameterize the stack frame Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 10/26] tcg-ppc64: Use the correct test in tcg_out_call Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 11/26] tcg-ppc64: Support the ppc64 elfv2 ABI Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 12/26] tcg-ppc64: Adjust tcg_out_call for ELFv2 Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 13/26] tcg-ppc64: Merge 32-bit ABIs into the prologue / frame code Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 14/26] tcg-ppc64: Fix sub2 implementation Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 15/26] tcg-ppc64: Begin merging ppc32 with ppc64 Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 16/26] tcg-ppc64: Merge ppc32 brcond2, setcond2, muluh Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 17/26] tcg-ppc64: Merge ppc32 qemu_ld/st Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 18/26] tcg-ppc64: Merge ppc32 register usage Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 19/26] tcg-ppc64: Support mulsh_i32 Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 20/26] tcg-ppc64: Merge ppc32 shifts Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 21/26] tcg-ppc: Remove the backend Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 22/26] tcg-ppc: Rename the tcg/ppc64 backend Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 23/26] qemu/osdep: Remove the need for qemu_init_auxval Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 24/26] tcg-ppc: Merge cache-utils into the backend Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 25/26] tcg-ppc64: Use the return address as a base pointer Richard Henderson
2014-05-01 15:44 ` [Qemu-devel] [PATCH 26/26] tcg-ppc: Streamline USE_DIRECT_JUMP Richard Henderson
2014-05-02 14:56 ` [Qemu-devel] [PATCH 00/26] Merge ppc32/ppc64 tcg backends Tom Musta
2014-05-02 16:30 ` Ulrich Weigand
2014-05-02 16:43   ` Richard Henderson
2014-05-05 20:32     ` Tom Musta

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