From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33111) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WgEX1-0003pP-DM for qemu-devel@nongnu.org; Fri, 02 May 2014 10:33:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WgEWt-0007AR-J6 for qemu-devel@nongnu.org; Fri, 02 May 2014 10:33:43 -0400 Received: from mail-ee0-x229.google.com ([2a00:1450:4013:c00::229]:35293) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WgEWt-0007AJ-CF for qemu-devel@nongnu.org; Fri, 02 May 2014 10:33:35 -0400 Received: by mail-ee0-f41.google.com with SMTP id d49so484905eek.0 for ; Fri, 02 May 2014 07:33:34 -0700 (PDT) Sender: Paolo Bonzini From: Paolo Bonzini Date: Fri, 2 May 2014 16:33:17 +0200 Message-Id: <1399041202-26184-4-git-send-email-pbonzini@redhat.com> In-Reply-To: <1399041202-26184-1-git-send-email-pbonzini@redhat.com> References: <1399041202-26184-1-git-send-email-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH v2 3/8] target-i386: fix set of registers zeroed on reset List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= BND0-3, BNDCFGU, BNDCFGS, BNDSTATUS were not zeroed on reset, but they should be (Intel Instruction Set Extensions Programming Reference 319433-015, pages 9-4 and 9-6). Same for YMM. XCR0 should be reset to 1. TSC and TSC_RESET were zeroed already by the memset, remove the explicit assignments. Cc: Andreas Färber Signed-off-by: Paolo Bonzini --- target-i386/cpu.c | 3 +-- target-i386/cpu.h | 11 ++++++----- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 05c3005..78c1573 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2477,8 +2477,7 @@ static void x86_cpu_reset(CPUState *s) cpu_breakpoint_remove_all(s, BP_CPU); cpu_watchpoint_remove_all(s, BP_CPU); - env->tsc_adjust = 0; - env->tsc = 0; + env->xcr0 = 1; #if !defined(CONFIG_USER_ONLY) /* We hard-wire the BSP to the first CPU. */ diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 2a22a7d..e2244e9 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -797,6 +797,10 @@ typedef struct CPUX86State { target_ulong cr[5]; /* NOTE: cr1 is unused */ int32_t a20_mask; + BNDReg bnd_regs[4]; + BNDCSReg bndcs_regs; + uint64_t msr_bndcfgs; + /* FPU state */ unsigned int fpstt; /* top of stack index */ uint16_t fpus; @@ -819,6 +823,8 @@ typedef struct CPUX86State { XMMReg xmm_t0; MMXReg mmx_t0; + XMMReg ymmh_regs[CPU_NB_REGS]; + /* sysenter registers */ uint32_t sysenter_cs; target_ulong sysenter_esp; @@ -928,12 +934,7 @@ typedef struct CPUX86State { uint16_t fpus_vmstate; uint16_t fptag_vmstate; uint16_t fpregs_format_vmstate; - uint64_t xstate_bv; - XMMReg ymmh_regs[CPU_NB_REGS]; - BNDReg bnd_regs[4]; - BNDCSReg bndcs_regs; - uint64_t msr_bndcfgs; uint64_t xcr0; -- 1.8.3.1