From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33182) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WgEXB-00042e-Jn for qemu-devel@nongnu.org; Fri, 02 May 2014 10:34:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WgEX2-0007D9-Ic for qemu-devel@nongnu.org; Fri, 02 May 2014 10:33:53 -0400 Received: from mail-ee0-x230.google.com ([2a00:1450:4013:c00::230]:57041) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WgEX2-0007D0-B6 for qemu-devel@nongnu.org; Fri, 02 May 2014 10:33:44 -0400 Received: by mail-ee0-f48.google.com with SMTP id e49so2044879eek.21 for ; Fri, 02 May 2014 07:33:43 -0700 (PDT) Received: from playground.lan (net-37-117-141-58.cust.vodafonedsl.it. [37.117.141.58]) by mx.google.com with ESMTPSA id x45sm5013195eeu.23.2014.05.02.07.33.41 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 02 May 2014 07:33:42 -0700 (PDT) Sender: Paolo Bonzini From: Paolo Bonzini Date: Fri, 2 May 2014 16:33:22 +0200 Message-Id: <1399041202-26184-9-git-send-email-pbonzini@redhat.com> In-Reply-To: <1399041202-26184-1-git-send-email-pbonzini@redhat.com> References: <1399041202-26184-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PATCH v2 8/8] x86: correctly implement soft reset List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Do not do a hard reset for port 92h, keyboard controller, or cf9h soft reset. These only reset the CPU. Reviewed-by: Anthony Liguori Signed-off-by: Paolo Bonzini --- hw/i386/pc.c | 3 ++- hw/input/pckbd.c | 5 +++-- hw/isa/lpc_ich9.c | 12 ++++++++++-- hw/pci-host/piix.c | 8 ++++++-- 4 files changed, 21 insertions(+), 7 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index a59e958..8716864 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -45,6 +45,7 @@ #include "kvm_i386.h" #include "hw/xen/xen.h" #include "sysemu/blockdev.h" +#include "sysemu/cpus.h" #include "hw/block/block.h" #include "ui/qemu-spice.h" #include "exec/memory.h" @@ -477,7 +478,7 @@ static void port92_write(void *opaque, hwaddr addr, uint64_t val, s->outport = val; qemu_set_irq(*s->a20_out, (val >> 1) & 1); if ((val & 1) && !(oldval & 1)) { - qemu_system_reset_request(); + cpu_soft_reset(); } } diff --git a/hw/input/pckbd.c b/hw/input/pckbd.c index 29af3d7..fd87776 100644 --- a/hw/input/pckbd.c +++ b/hw/input/pckbd.c @@ -26,6 +26,7 @@ #include "hw/i386/pc.h" #include "hw/input/ps2.h" #include "sysemu/sysemu.h" +#include "sysemu/cpus.h" /* debug PC keyboard */ //#define DEBUG_KBD @@ -220,7 +221,7 @@ static void outport_write(KBDState *s, uint32_t val) qemu_set_irq(*s->a20_out, (val >> 1) & 1); } if (!(val & 1)) { - qemu_system_reset_request(); + cpu_soft_reset(); } } @@ -299,7 +300,7 @@ static void kbd_write_command(void *opaque, hwaddr addr, s->outport &= ~KBD_OUT_A20; break; case KBD_CCMD_RESET: - qemu_system_reset_request(); + cpu_soft_reset(); break; case KBD_CCMD_NO_OP: /* ignore that */ diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 51ce12d..e9fde85 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -45,6 +45,7 @@ #include "hw/pci/pci_bus.h" #include "exec/address-spaces.h" #include "sysemu/sysemu.h" +#include "sysemu/cpus.h" static int ich9_lpc_sci_irq(ICH9LPCState *lpc); @@ -507,8 +508,15 @@ static void ich9_rst_cnt_write(void *opaque, hwaddr addr, uint64_t val, ICH9LPCState *lpc = opaque; if (val & 4) { - qemu_system_reset_request(); - return; + /* In a real ICH9, FULL_RST affects whether the hardware goes to S5 + * for 3-5 seconds, but is not enough alone; you need to set SYS_RST + * too. + */ + if (val & 2) { + qemu_system_reset_request(); + } else { + cpu_soft_reset(); + } } lpc->rst_cnt = val & 0xA; /* keep FULL_RST (bit 3) and SYS_RST (bit 1) */ } diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c index ffdc853..1e60172 100644 --- a/hw/pci-host/piix.c +++ b/hw/pci-host/piix.c @@ -34,6 +34,7 @@ #include "sysemu/sysemu.h" #include "hw/i386/ioapic.h" #include "qapi/visitor.h" +#include "sysemu/cpus.h" /* * I440FX chipset data sheet. @@ -587,8 +588,11 @@ static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len) PIIX3State *d = opaque; if (val & 4) { - qemu_system_reset_request(); - return; + if (val & 2) { + qemu_system_reset_request(); + } else { + cpu_soft_reset(); + } } d->rcr = val & 2; /* keep System Reset type only */ } -- 1.8.3.1