[Qemu-devel] [PATCH 1/3] timer: add EFM32 timer

[Qemu-devel] [PATCH 1/3] timer: add EFM32 timer

[Rabin Vincent]

Add support for the TIMER block on the EFM32GG.

Signed-off-by: Rabin Vincent <rabin@rab.in>
---
 hw/timer/Makefile.objs |   1 +
 hw/timer/efm32-timer.c | 204 +++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 205 insertions(+)
 create mode 100644 hw/timer/efm32-timer.c

diff --git a/hw/timer/Makefile.objs b/hw/timer/Makefile.objs
index 2c86c3d..440d4ec 100644
--- a/hw/timer/Makefile.objs
+++ b/hw/timer/Makefile.objs
@@ -18,6 +18,7 @@ common-obj-$(CONFIG_IMX) += imx_gpt.o
 common-obj-$(CONFIG_LM32) += lm32_timer.o
 common-obj-$(CONFIG_MILKYMIST) += milkymist-sysctl.o
 
+obj-$(CONFIG_EFM32) += efm32-timer.o
 obj-$(CONFIG_EXYNOS4) += exynos4210_mct.o
 obj-$(CONFIG_EXYNOS4) += exynos4210_pwm.o
 obj-$(CONFIG_EXYNOS4) += exynos4210_rtc.o
diff --git a/hw/timer/efm32-timer.c b/hw/timer/efm32-timer.c
new file mode 100644
index 0000000..bbceb43
--- /dev/null
+++ b/hw/timer/efm32-timer.c
@@ -0,0 +1,204 @@
+/*
+ * EFM32GG Timer
+ *
+ * Copyright (C) 2014 Rabin Vincent <rabin@rab.in>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "hw/sysbus.h"
+#include "sysemu/sysemu.h"
+#include "qemu/timer.h"
+
+enum {
+    TIMER_CTRL              = 0x00,
+    TIMER_CMD               = 0x04,
+    TIMER_IEN               = 0x0C,
+    TIMER_IF                = 0x10,
+    TIMER_IFS               = 0x14,
+    TIMER_IFC               = 0x18,
+    TIMER_CNT               = 0x24,
+    TIMER_REG_SIZE          = TIMER_CNT + 4,
+
+    TIMER_CTRL_MODE_UP      = 0x0,
+    TIMER_CTRL_MODE_DOWN    = 0x1,
+
+    TIMER_CMD_START         = 1 << 0,
+    TIMER_CMD_STOP          = 1 << 1,
+
+    TIMER_IF_OF             = 1 << 0,
+    TIMER_IF_UF             = 1 << 1,
+};
+
+#define REG(s, x) (s->regs[(x) / 4])
+
+#define TYPE_EFM32_TIMER "efm32-timer"
+#define EFM32_TIMER(obj) \
+    OBJECT_CHECK(Efm32TimerState, (obj), TYPE_EFM32_TIMER)
+
+typedef struct Efm32TimerState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion iomem;
+    uint32_t rate;
+    QEMUTimer *timer;
+    uint32_t regs[TIMER_REG_SIZE / 4];
+    qemu_irq irq;
+} Efm32TimerState;
+
+#define HFPERCLK_RATE 48000000
+
+static uint64_t timer_to_ns(Efm32TimerState *s, uint64_t value)
+{
+    return muldiv64(value, get_ticks_per_sec(), s->rate);
+}
+
+static uint64_t ns_to_timer(Efm32TimerState *s, uint64_t value)
+{
+    return muldiv64(value, s->rate, get_ticks_per_sec());
+}
+
+static uint32_t timer_mode(Efm32TimerState *s)
+{
+    return REG(s, TIMER_CTRL) & 0x3;
+}
+
+static void timer_update_irq(Efm32TimerState *s)
+{
+    qemu_set_irq(s->irq, REG(s, TIMER_IF) & REG(s, TIMER_IEN));
+}
+
+static void timer_tick(void *opaque)
+{
+    Efm32TimerState *s = opaque;
+    uint32_t flag;
+
+    if (timer_mode(s) == TIMER_CTRL_MODE_UP) {
+        flag = TIMER_IF_OF;
+    } else {
+        flag = TIMER_IF_UF;
+    }
+
+    REG(s, TIMER_IF) |= flag;
+
+    timer_update_irq(s);
+}
+
+static uint64_t timer_read(void *opaque, hwaddr offset,
+                          unsigned size)
+{
+    Efm32TimerState *s = opaque;
+
+    switch (offset) {
+    case TIMER_CTRL:
+        return REG(s, TIMER_CTRL);
+    case TIMER_IEN:
+        return REG(s, TIMER_IEN);
+    case TIMER_IF:
+        return REG(s, TIMER_IF);
+    case TIMER_CNT:
+        return ns_to_timer(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
+    }
+
+    return 0;
+}
+
+static void timer_write(void *opaque, hwaddr offset,
+                       uint64_t value, unsigned size)
+{
+    Efm32TimerState *s = opaque;
+
+    switch (offset) {
+    case TIMER_CTRL:
+        REG(s, TIMER_CTRL) = value;
+        s->rate = HFPERCLK_RATE / (1 << ((value >> 24) & 0xff));
+        break;
+    case TIMER_IEN:
+        REG(s, TIMER_IEN) = value;
+        break;
+    case TIMER_IFS:
+        REG(s, TIMER_IF) |= value;
+        break;
+    case TIMER_IFC:
+        REG(s, TIMER_IF) &= ~value;
+        break;
+    case TIMER_CMD:
+        if (value & TIMER_CMD_START) {
+            uint32_t expiry;
+
+            if (timer_mode(s) == TIMER_CTRL_MODE_UP) {
+                expiry = 0xffffffff - REG(s, TIMER_CNT);
+            } else if (timer_mode(s) == TIMER_CTRL_MODE_DOWN) {
+                expiry = REG(s, TIMER_CNT);
+            }
+
+            timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) \
+                                + timer_to_ns(s, expiry));
+        } else if (value & TIMER_CMD_STOP) {
+            timer_del(s->timer);
+        }
+        break;
+    case TIMER_CNT:
+        REG(s, TIMER_CNT) = value;
+        break;
+    }
+
+    timer_update_irq(s);
+}
+
+static const MemoryRegionOps timer_ops = {
+    .read = timer_read,
+    .write = timer_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static const VMStateDescription vmstate_efm32_timer = {
+    .name = "efm32-timer",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .minimum_version_id_old = 1,
+    .fields      = (VMStateField[]) {
+        VMSTATE_UINT32(rate, Efm32TimerState),
+        VMSTATE_TIMER(timer, Efm32TimerState),
+        VMSTATE_UINT32_ARRAY(regs, Efm32TimerState, TIMER_REG_SIZE / 4),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static int efm32_timer_init(SysBusDevice *sbd)
+{
+    DeviceState *dev = DEVICE(sbd);
+    Efm32TimerState *s = EFM32_TIMER(dev);
+
+    sysbus_init_irq(sbd, &s->irq);
+
+    memory_region_init_io(&s->iomem, OBJECT(s), &timer_ops, s,
+                          "timer", 0x400);
+    sysbus_init_mmio(sbd, &s->iomem);
+
+    s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, timer_tick, s);
+    vmstate_register(dev, -1, &vmstate_efm32_timer, s);
+    return 0;
+}
+
+static void efm32_timer_class_init(ObjectClass *klass, void *data)
+{
+    SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
+
+    sdc->init = efm32_timer_init;
+}
+
+static const TypeInfo efm32_timer_info = {
+    .name          = TYPE_EFM32_TIMER,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(Efm32TimerState),
+    .class_init    = efm32_timer_class_init,
+};
+
+static void efm32_register_types(void)
+{
+    type_register_static(&efm32_timer_info);
+}
+
+type_init(efm32_register_types)
-- 
2.0.0.rc0

[Qemu-devel] [PATCH 2/3] char: add EFM32 UART

[Rabin Vincent]

Add support for the UART block on the EFM32GG.

Signed-off-by: Rabin Vincent <rabin@rab.in>
---
 hw/char/Makefile.objs |   1 +
 hw/char/efm32-uart.c  | 217 ++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 218 insertions(+)
 create mode 100644 hw/char/efm32-uart.c

diff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs
index 317385d..7261569 100644
--- a/hw/char/Makefile.objs
+++ b/hw/char/Makefile.objs
@@ -9,6 +9,7 @@ common-obj-$(CONFIG_XILINX) += xilinx_uartlite.o
 common-obj-$(CONFIG_XEN_BACKEND) += xen_console.o
 common-obj-$(CONFIG_CADENCE) += cadence_uart.o
 
+obj-$(CONFIG_EFM32) += efm32-uart.o
 obj-$(CONFIG_EXYNOS4) += exynos4210_uart.o
 obj-$(CONFIG_COLDFIRE) += mcf_uart.o
 obj-$(CONFIG_OMAP) += omap_uart.o
diff --git a/hw/char/efm32-uart.c b/hw/char/efm32-uart.c
new file mode 100644
index 0000000..bca433f
--- /dev/null
+++ b/hw/char/efm32-uart.c
@@ -0,0 +1,217 @@
+/*
+ * EFM32GG UART
+ *
+ * Copyright (c) 2014 Rabin Vincent <rabin@rab.in>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "hw/hw.h"
+#include "hw/sysbus.h"
+#include "sysemu/char.h"
+
+enum {
+    UARTn_CMD               = 0x0c,
+    UARTn_STATUS            = 0x10,
+    UARTn_RXDATAX           = 0x18,
+    UARTn_TXDATA            = 0x34,
+    UARTn_IF                = 0x40,
+    UARTn_IFS               = 0x44,
+    UARTn_IFC               = 0x48,
+    UARTn_IEN               = 0x4c,
+    UARTn_REG_SIZE          = UARTn_IEN + 4,
+
+    UARTn_STATUS_TXBL       = 1 << 6,
+    UARTn_STATUS_RXFULL     = 1 << 8,
+    UARTn_STATUS_RXDATAV    = 1 << 7,
+
+    UARTn_RXDATAX_FERR      = 1 << 15,
+
+    UARTn_IF_RXDATAV        = 1 << 2,
+};
+
+#define REG(s, x) (s->regs[(x) / 4])
+
+#define TYPE_EFM32_UART "efm32-uart"
+#define EFM32_UART(obj) \
+    OBJECT_CHECK(Efm32UartState, (obj), TYPE_EFM32_UART)
+
+struct Efm32UartState {
+    SysBusDevice parent_obj;
+
+    MemoryRegion regs_region;
+    CharDriverState *chr;
+    qemu_irq rxirq;
+    qemu_irq txirq;
+
+    uint32_t regs[UARTn_REG_SIZE / 4];
+};
+
+typedef struct Efm32UartState Efm32UartState;
+
+static void efm32_uart_update_irq(Efm32UartState *s)
+{
+    if (REG(s, UARTn_STATUS) & UARTn_STATUS_RXDATAV) {
+        REG(s, UARTn_IF) |= UARTn_IF_RXDATAV;
+    } else {
+        REG(s, UARTn_IF) &= ~UARTn_IF_RXDATAV;
+    }
+
+    qemu_set_irq(s->rxirq, REG(s, UARTn_IF) & \
+                           REG(s, UARTn_IEN) & \
+                           UARTn_IF_RXDATAV);
+}
+
+static uint64_t efm32_uart_read(void *opaque, hwaddr addr, unsigned size)
+{
+    Efm32UartState *s = opaque;
+    uint32_t r = 0;
+
+    switch (addr) {
+    case UARTn_STATUS:
+        return REG(s, UARTn_STATUS);
+    case UARTn_RXDATAX:
+        REG(s, UARTn_STATUS) &= ~UARTn_STATUS_RXDATAV;
+        return REG(s, UARTn_RXDATAX);
+    case UARTn_IF:
+        return REG(s, UARTn_IF);
+    case UARTn_IEN:
+        return REG(s, UARTn_IEN);
+    }
+
+    efm32_uart_update_irq(s);
+
+    return r;
+}
+
+static void efm32_uart_write(void *opaque, hwaddr addr,
+                             uint64_t value, unsigned size)
+{
+    Efm32UartState *s = opaque;
+    unsigned char ch = value;
+
+    switch (addr) {
+    case UARTn_TXDATA:
+        if (s->chr) {
+            qemu_chr_fe_write(s->chr, &ch, 1);
+        }
+        break;
+    case UARTn_IFS:
+        REG(s, UARTn_IF) |= value;
+        break;
+    case UARTn_IFC:
+        REG(s, UARTn_IF) &= ~value;
+        break;
+    case UARTn_IEN:
+        REG(s, UARTn_IEN) = value;
+        break;
+    }
+
+    efm32_uart_update_irq(s);
+}
+
+static const MemoryRegionOps uart_mmio_ops = {
+    .read = efm32_uart_read,
+    .write = efm32_uart_write,
+    .valid = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
+    .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
+static void efm32_uart_rx(void *opaque, const uint8_t *buf, int size)
+{
+    Efm32UartState *s = opaque;
+
+    REG(s, UARTn_STATUS) |= UARTn_STATUS_RXDATAV;
+    REG(s, UARTn_RXDATAX) = *buf;
+
+    efm32_uart_update_irq(s);
+}
+
+static int efm32_uart_can_rx(void *opaque)
+{
+    Efm32UartState *s = opaque;
+
+    return !(REG(s, UARTn_STATUS) & UARTn_STATUS_RXDATAV);
+}
+
+static void efm32_uart_event(void *opaque, int event)
+{
+    Efm32UartState *s = opaque;
+
+    if (event == CHR_EVENT_BREAK) {
+        REG(s, UARTn_STATUS) |= UARTn_STATUS_RXDATAV;
+        REG(s, UARTn_RXDATAX) = UARTn_RXDATAX_FERR;
+        efm32_uart_update_irq(s);
+    }
+}
+
+static void efm32_uart_reset(DeviceState *d)
+{
+    Efm32UartState *s = EFM32_UART(d);
+
+    memset(&s->regs, 0, sizeof(s->regs));
+    REG(s, UARTn_STATUS) |= UARTn_STATUS_TXBL;
+}
+
+static void efm32_uart_realize(DeviceState *dev, Error **errp)
+{
+    Efm32UartState *s = EFM32_UART(dev);
+
+    s->chr = qemu_char_get_next_serial();
+    if (s->chr) {
+        qemu_chr_add_handlers(s->chr, efm32_uart_can_rx, efm32_uart_rx,
+                              efm32_uart_event, s);
+    }
+}
+
+static void efm32_uart_init(Object *obj)
+{
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+    Efm32UartState *s = EFM32_UART(obj);
+
+    sysbus_init_irq(sbd, &s->rxirq);
+    sysbus_init_irq(sbd, &s->txirq);
+
+    memory_region_init_io(&s->regs_region, OBJECT(s), &uart_mmio_ops, s,
+                          "efm32-uart", UARTn_REG_SIZE);
+    sysbus_init_mmio(sbd, &s->regs_region);
+}
+
+static const VMStateDescription vmstate_efm32_uart = {
+    .name = "efm32-uart",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .minimum_version_id_old = 1,
+    .fields      = (VMStateField[]) {
+        VMSTATE_UINT32_ARRAY(regs, Efm32UartState, UARTn_REG_SIZE / 4),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
+static void efm32_uart_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->realize = efm32_uart_realize;
+    dc->reset = efm32_uart_reset;
+    dc->vmsd = &vmstate_efm32_uart;
+}
+
+static const TypeInfo efm32_uart_info = {
+    .name          = TYPE_EFM32_UART,
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(Efm32UartState),
+    .instance_init = efm32_uart_init,
+    .class_init    = efm32_uart_class_init,
+};
+
+static void efm32_uart_register_types(void)
+{
+    type_register_static(&efm32_uart_info);
+}
+
+type_init(efm32_uart_register_types)
-- 
2.0.0.rc0

[Qemu-devel] [PATCH 3/3] arm: add EFM32GG-DK3750 support

[Rabin Vincent]

Add support for the EFM32GG990 MCU and its development board
EFM32GG-DK3750.  This is a Cortex-M3 platform supported
by mainline Linux.

Signed-off-by: Rabin Vincent <rabin@rab.in>
---
 default-configs/arm-softmmu.mak |  1 +
 hw/arm/Makefile.objs            |  1 +
 hw/arm/efm32.c                  | 71 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 73 insertions(+)
 create mode 100644 hw/arm/efm32.c

diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index f3513fa..d151f27 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -57,6 +57,7 @@ CONFIG_PL310=y
 CONFIG_PL330=y
 CONFIG_CADENCE=y
 CONFIG_XGMAC=y
+CONFIG_EFM32=y
 CONFIG_EXYNOS4=y
 CONFIG_PXA2XX=y
 CONFIG_BITBANG_I2C=y
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 6088e53..7030a82 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -6,5 +6,6 @@ obj-y += tosa.o versatilepb.o vexpress.o virt.o xilinx_zynq.o z2.o
 
 obj-y += armv7m.o exynos4210.o pxa2xx.o pxa2xx_gpio.o pxa2xx_pic.o
 obj-$(CONFIG_DIGIC) += digic.o
+obj-$(CONFIG_EFM32) += efm32.o
 obj-y += omap1.o omap2.o strongarm.o
 obj-$(CONFIG_ALLWINNER_A10) += allwinner-a10.o cubieboard.o
diff --git a/hw/arm/efm32.c b/hw/arm/efm32.c
new file mode 100644
index 0000000..201f921
--- /dev/null
+++ b/hw/arm/efm32.c
@@ -0,0 +1,71 @@
+/*
+ * EFM32GG
+ *
+ * Copyright (C) 2014 Rabin Vincent <rabin@rab.in>
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ */
+
+#include "hw/sysbus.h"
+#include "hw/arm/arm.h"
+#include "hw/devices.h"
+#include "hw/boards.h"
+#include "hw/block/flash.h"
+#include "exec/address-spaces.h"
+
+static void efm32_init(QEMUMachineInitArgs *args)
+{
+    static const int timer_irq[] = {2, 12, 13, 14};
+    const char *cpu_model = args->cpu_model;
+    const char *kernel_filename = args->kernel_filename;
+    MemoryRegion *address_space_mem = get_system_memory();
+    qemu_irq *pic;
+    int i;
+    MemoryRegion *nor = g_new(MemoryRegion, 1);
+    MemoryRegion *psram = g_new(MemoryRegion, 1);
+    DriveInfo *dinfo;
+    uint32_t flashsize = 16 * 1024 * 1024;
+
+    pic = armv7m_init(address_space_mem, 1024, 128, kernel_filename, cpu_model);
+
+    memory_region_init_ram(psram, NULL, "psram", 4 * 1024 * 1024);
+    vmstate_register_ram_global(psram);
+    memory_region_add_subregion(address_space_mem, 0x88000000, psram);
+
+    memory_region_init_ram(nor, NULL, "flash", flashsize);
+    vmstate_register_ram_global(nor);
+    memory_region_add_subregion(address_space_mem, 0x8C000000, nor);
+    memory_region_set_readonly(nor, true);
+
+    sysbus_create_varargs("efm32-uart", 0x4000e400, pic[22], pic[23], NULL);
+    for (i = 0; i < 4; i++) {
+        sysbus_create_simple("efm32-timer", 0x40010000 + i * 0x400,
+                             pic[timer_irq[i]]);
+    }
+
+    dinfo = drive_get(IF_PFLASH, 0, 0);
+    if (dinfo) {
+        int sector_len = 128 * 1024;
+        if (!pflash_cfi01_register(0x8c000000, NULL, "dk.flash", flashsize,
+                                   dinfo ? dinfo->bdrv : NULL,
+                                   sector_len, flashsize / sector_len,
+                                   2, 0, 0, 0, 0, 0)) {
+            fprintf(stderr, "qemu: Error registering flash memory.\n");
+            exit(1);
+        }
+    }
+}
+
+static QEMUMachine efm32ggdk3750_machine = {
+    .name = "efm32ggdk3750",
+    .desc = "EnergyMicro Giant Gecko Development Kit",
+    .init = efm32_init,
+};
+
+static void efm32_machine_init(void)
+{
+    qemu_register_machine(&efm32ggdk3750_machine);
+}
+
+machine_init(efm32_machine_init);
-- 
2.0.0.rc0

Re: [Qemu-devel] [PATCH 3/3] arm: add EFM32GG-DK3750 support

[Andreas Färber]

Hi,

Am 04.05.2014 17:52, schrieb Rabin Vincent:
> Add support for the EFM32GG990 MCU and its development board
> EFM32GG-DK3750.  This is a Cortex-M3 platform supported
> by mainline Linux.
> 
> Signed-off-by: Rabin Vincent <rabin@rab.in>
> ---
>  default-configs/arm-softmmu.mak |  1 +
>  hw/arm/Makefile.objs            |  1 +
>  hw/arm/efm32.c                  | 71 +++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 73 insertions(+)
>  create mode 100644 hw/arm/efm32.c

Apart from a missing cover letter to reply to, the preceding two devices
look good to me - this machine however is copying the wrong code. For
one, no semicolon after machine_init() please ;) and more importantly
please follow the example set by Canon A1000 and Allwinner A10 for SoC
vs. machine modeling. Not only does it help clarify what is actually on
the board and what on the chip and facilitates reuse by future EFM32
based boards, it also helps with the technical conversion to QOM realize
and the QOM composition tree.

Thanks,
Andreas

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