From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55254) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WhYhD-00043S-NK for qemu-devel@nongnu.org; Tue, 06 May 2014 02:17:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WhYh7-0002xd-Nk for qemu-devel@nongnu.org; Tue, 06 May 2014 02:17:43 -0400 Received: from mail-qc0-x22b.google.com ([2607:f8b0:400d:c01::22b]:63640) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WhYh7-0002xZ-JA for qemu-devel@nongnu.org; Tue, 06 May 2014 02:17:37 -0400 Received: by mail-qc0-f171.google.com with SMTP id x13so890877qcv.30 for ; Mon, 05 May 2014 23:17:37 -0700 (PDT) From: "Edgar E. Iglesias" Date: Tue, 6 May 2014 16:08:17 +1000 Message-Id: <1399356506-5609-14-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1399356506-5609-1-git-send-email-edgar.iglesias@gmail.com> References: <1399356506-5609-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v1 13/22] target-arm: Register EL2 versions of ELR and SPSR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com, john.williams@xilinx.com, alex.bennee@linaro.org, agraf@suse.de From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias --- target-arm/helper.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index ba1830d..8efc340 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2078,6 +2078,19 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { REGINFO_SENTINEL }; +static const ARMCPRegInfo v8_el2_cp_reginfo[] = { + { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64, + .type = ARM_CP_NO_MIGRATE, + .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, + .access = PL2_RW, + .fieldoffset = offsetof(CPUARMState, elr_el[ELR_EL_IDX(2)]) }, + { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64, + .type = ARM_CP_NO_MIGRATE, + .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0, + .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[6]) }, + REGINFO_SENTINEL +}; + static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -2321,6 +2334,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, v8_idregs); define_arm_cp_regs(cpu, v8_cp_reginfo); define_aarch64_debug_regs(cpu); + + if (arm_feature(env, ARM_FEATURE_EL2)) { + define_arm_cp_regs(cpu, v8_el2_cp_reginfo); + } } if (arm_feature(env, ARM_FEATURE_MPU)) { /* These are the MPU registers prior to PMSAv6. Any new -- 1.8.3.2