From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55437) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WhYhr-00052p-Uo for qemu-devel@nongnu.org; Tue, 06 May 2014 02:18:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WhYhl-00033x-7x for qemu-devel@nongnu.org; Tue, 06 May 2014 02:18:23 -0400 Received: from mail-qc0-x22a.google.com ([2607:f8b0:400d:c01::22a]:41862) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WhYhl-00033r-4D for qemu-devel@nongnu.org; Tue, 06 May 2014 02:18:17 -0400 Received: by mail-qc0-f170.google.com with SMTP id i8so2162165qcq.15 for ; Mon, 05 May 2014 23:18:16 -0700 (PDT) From: "Edgar E. Iglesias" Date: Tue, 6 May 2014 16:08:18 +1000 Message-Id: <1399356506-5609-15-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1399356506-5609-1-git-send-email-edgar.iglesias@gmail.com> References: <1399356506-5609-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v1 14/22] target-arm: Register EL3 versions of ELR and SPSR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com, john.williams@xilinx.com, alex.bennee@linaro.org, agraf@suse.de From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias --- target-arm/helper.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/target-arm/helper.c b/target-arm/helper.c index 8efc340..65daeaf 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -2091,6 +2091,19 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = { REGINFO_SENTINEL }; +static const ARMCPRegInfo v8_el3_cp_reginfo[] = { + { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64, + .type = ARM_CP_NO_MIGRATE, + .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1, + .access = PL3_RW, + .fieldoffset = offsetof(CPUARMState, elr_el[ELR_EL_IDX(3)]) }, + { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64, + .type = ARM_CP_NO_MIGRATE, + .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0, + .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[7]) }, + REGINFO_SENTINEL +}; + static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -2338,6 +2351,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_EL2)) { define_arm_cp_regs(cpu, v8_el2_cp_reginfo); } + if (arm_feature(env, ARM_FEATURE_EL3)) { + define_arm_cp_regs(cpu, v8_el3_cp_reginfo); + } } if (arm_feature(env, ARM_FEATURE_MPU)) { /* These are the MPU registers prior to PMSAv6. Any new -- 1.8.3.2