From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52969) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WhYar-0003Dq-0P for qemu-devel@nongnu.org; Tue, 06 May 2014 02:11:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WhYak-0000g5-JU for qemu-devel@nongnu.org; Tue, 06 May 2014 02:11:08 -0400 Received: from mail-qc0-x235.google.com ([2607:f8b0:400d:c01::235]:47299) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WhYak-0000fu-F7 for qemu-devel@nongnu.org; Tue, 06 May 2014 02:11:02 -0400 Received: by mail-qc0-f181.google.com with SMTP id m20so5749801qcx.12 for ; Mon, 05 May 2014 23:11:02 -0700 (PDT) From: "Edgar E. Iglesias" Date: Tue, 6 May 2014 16:08:07 +1000 Message-Id: <1399356506-5609-4-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1399356506-5609-1-git-send-email-edgar.iglesias@gmail.com> References: <1399356506-5609-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v1 03/22] target-arm: Make esr_el1 an array List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com, john.williams@xilinx.com, alex.bennee@linaro.org, agraf@suse.de From: "Edgar E. Iglesias" No functional change. Prepares for future addtion of EL2 and 3 versions of this reg. Signed-off-by: Edgar E. Iglesias --- target-arm/cpu.h | 3 ++- target-arm/helper-a64.c | 4 ++-- target-arm/helper.c | 11 ++++++----- 3 files changed, 10 insertions(+), 8 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index eb7a0f5..2a068ec 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -186,7 +186,8 @@ typedef struct CPUARMState { uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ uint32_t ifsr_el2; /* Fault status registers. */ - uint64_t esr_el1; +#define ESR_EL_IDX(x) (x - 1) + uint64_t esr_el[1]; uint32_t c6_region[8]; /* MPU base/size registers. */ uint64_t far_el1; /* Fault address registers. */ uint64_t par_el1; /* Translation result. */ diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c index 5adf2b5..4bee075 100644 --- a/target-arm/helper-a64.c +++ b/target-arm/helper-a64.c @@ -464,7 +464,7 @@ void aarch64_cpu_do_interrupt(CPUState *cs) env->exception.syndrome); } - env->cp15.esr_el1 = env->exception.syndrome; + env->cp15.esr_el[ESR_EL_IDX(1)] = env->exception.syndrome; env->cp15.far_el1 = env->exception.vaddress; switch (cs->exception_index) { @@ -495,7 +495,7 @@ void aarch64_cpu_do_interrupt(CPUState *cs) } else { env->banked_spsr[0] = cpsr_read(env); if (!env->thumb) { - env->cp15.esr_el1 |= 1 << 25; + env->cp15.esr_el[ESR_EL_IDX(1)] |= 1 << 25; } env->elr_el[ELR_EL_IDX(1)] = env->regs[15]; diff --git a/target-arm/helper.c b/target-arm/helper.c index 3457d3e..c86fab6 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1452,7 +1452,7 @@ static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri, static const ARMCPRegInfo vmsa_cp_reginfo[] = { { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, - .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el1), + .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[ESR_EL_IDX(1)]), .resetfn = arm_cp_reset_ignore, }, { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW, @@ -1460,7 +1460,8 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64, .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0, .access = PL1_RW, - .fieldoffset = offsetof(CPUARMState, cp15.esr_el1), .resetvalue = 0, }, + .fieldoffset = offsetof(CPUARMState, cp15.esr_el[ESR_EL_IDX(1)]), + .resetvalue = 0, }, { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1), @@ -1521,7 +1522,7 @@ static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri, static const ARMCPRegInfo omap_cp_reginfo[] = { { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE, - .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el1), + .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[ESR_EL_IDX(1)]), .resetvalue = 0, }, { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .type = ARM_CP_NOP }, @@ -3331,11 +3332,11 @@ void arm_cpu_do_interrupt(CPUState *cs) offset = 4; break; case EXCP_DATA_ABORT: - env->cp15.esr_el1 = env->exception.fsr; + env->cp15.esr_el[ESR_EL_IDX(1)] = env->exception.fsr; env->cp15.far_el1 = deposit64(env->cp15.far_el1, 0, 32, env->exception.vaddress); qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n", - (uint32_t)env->cp15.esr_el1, + (uint32_t)env->cp15.esr_el[ESR_EL_IDX(1)], (uint32_t)env->exception.vaddress); new_mode = ARM_CPU_MODE_ABT; addr = 0x10; -- 1.8.3.2