From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53139) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WhYbV-0004A4-EZ for qemu-devel@nongnu.org; Tue, 06 May 2014 02:11:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WhYbO-0000r1-Kk for qemu-devel@nongnu.org; Tue, 06 May 2014 02:11:49 -0400 Received: from mail-qc0-x236.google.com ([2607:f8b0:400d:c01::236]:41841) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WhYbO-0000qx-Ft for qemu-devel@nongnu.org; Tue, 06 May 2014 02:11:42 -0400 Received: by mail-qc0-f182.google.com with SMTP id e16so6433841qcx.27 for ; Mon, 05 May 2014 23:11:42 -0700 (PDT) From: "Edgar E. Iglesias" Date: Tue, 6 May 2014 16:08:08 +1000 Message-Id: <1399356506-5609-5-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1399356506-5609-1-git-send-email-edgar.iglesias@gmail.com> References: <1399356506-5609-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v1 04/22] target-arm: c12_vbar -> vbar_el[] List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com, john.williams@xilinx.com, alex.bennee@linaro.org, agraf@suse.de From: "Edgar E. Iglesias" No functional change. Preparation for adding EL2 and 3 versions of this reg. Signed-off-by: Edgar E. Iglesias --- target-arm/cpu.h | 3 ++- target-arm/helper-a64.c | 2 +- target-arm/helper.c | 6 +++--- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 2a068ec..ff86250 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -200,7 +200,8 @@ typedef struct CPUARMState { uint32_t c9_pmuserenr; /* perf monitor user enable */ uint32_t c9_pminten; /* perf monitor interrupt enables */ uint64_t mair_el1; - uint64_t c12_vbar; /* vector base address register */ +#define VBAR_EL_IDX(x) (x - 1) + uint64_t vbar_el[1]; /* vector base address register */ uint32_t c13_fcse; /* FCSE PID. */ uint64_t contextidr_el1; /* Context ID. */ uint64_t tpidr_el0; /* User RW Thread register. */ diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c index 4bee075..10bd1fc 100644 --- a/target-arm/helper-a64.c +++ b/target-arm/helper-a64.c @@ -443,7 +443,7 @@ void aarch64_cpu_do_interrupt(CPUState *cs) { ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; - target_ulong addr = env->cp15.c12_vbar; + target_ulong addr = env->cp15.vbar_el[VBAR_EL_IDX(1)]; int i; if (arm_current_pl(env) == 0) { diff --git a/target-arm/helper.c b/target-arm/helper.c index c86fab6..baeaa28 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -657,7 +657,7 @@ static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri, * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7 * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.) */ - env->cp15.c12_vbar = value & ~0x1FULL; + env->cp15.vbar_el[VBAR_EL_IDX(1)] = value & ~0x1FULL; } static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -766,7 +766,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { { .name = "VBAR", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .writefn = vbar_write, - .fieldoffset = offsetof(CPUARMState, cp15.c12_vbar), + .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[VBAR_EL_IDX(1)]), .resetvalue = 0 }, { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr), @@ -3373,7 +3373,7 @@ void arm_cpu_do_interrupt(CPUState *cs) * and is never in monitor mode this feature is always active. * Note: only bits 31:5 are valid. */ - addr += env->cp15.c12_vbar; + addr += env->cp15.vbar_el[VBAR_EL_IDX(1)]; } switch_mode (env, new_mode); env->spsr = cpsr_read(env); -- 1.8.3.2