From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53729) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WhYdP-0006qp-2X for qemu-devel@nongnu.org; Tue, 06 May 2014 02:13:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WhYdJ-0001IG-0N for qemu-devel@nongnu.org; Tue, 06 May 2014 02:13:47 -0400 Received: from mail-qc0-x22a.google.com ([2607:f8b0:400d:c01::22a]:46840) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WhYdI-0001I7-TN for qemu-devel@nongnu.org; Tue, 06 May 2014 02:13:40 -0400 Received: by mail-qc0-f170.google.com with SMTP id i8so2185255qcq.29 for ; Mon, 05 May 2014 23:13:40 -0700 (PDT) From: "Edgar E. Iglesias" Date: Tue, 6 May 2014 16:08:11 +1000 Message-Id: <1399356506-5609-8-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1399356506-5609-1-git-send-email-edgar.iglesias@gmail.com> References: <1399356506-5609-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH v1 07/22] target-arm: A64: Add SP entries for EL2 and 3 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, peter.maydell@linaro.org Cc: rob.herring@linaro.org, peter.crosthwaite@xilinx.com, john.williams@xilinx.com, alex.bennee@linaro.org, agraf@suse.de From: "Edgar E. Iglesias" Signed-off-by: Edgar E. Iglesias --- target-arm/cpu.h | 2 +- target-arm/machine.c | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 938f389..7bac416 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -164,7 +164,7 @@ typedef struct CPUARMState { #define ELR_EL_IDX(x) (x - 1) uint64_t elr_el[1]; /* AArch64 exception link regs */ - uint64_t sp_el[2]; /* AArch64 banked stack pointers */ + uint64_t sp_el[4]; /* AArch64 banked stack pointers */ /* System control coprocessor (cp15) */ struct { diff --git a/target-arm/machine.c b/target-arm/machine.c index 8b299a0..6a87ef6 100644 --- a/target-arm/machine.c +++ b/target-arm/machine.c @@ -222,9 +222,9 @@ static int cpu_post_load(void *opaque, int version_id) const VMStateDescription vmstate_arm_cpu = { .name = "cpu", - .version_id = 17, - .minimum_version_id = 17, - .minimum_version_id_old = 17, + .version_id = 18, + .minimum_version_id = 18, + .minimum_version_id_old = 18, .pre_save = cpu_pre_save, .post_load = cpu_post_load, .fields = (VMStateField[]) { @@ -244,7 +244,7 @@ const VMStateDescription vmstate_arm_cpu = { VMSTATE_UINT32_ARRAY(env.usr_regs, ARMCPU, 5), VMSTATE_UINT32_ARRAY(env.fiq_regs, ARMCPU, 5), VMSTATE_UINT64(env.elr_el[ELR_EL_IDX(1)], ARMCPU), - VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 2), + VMSTATE_UINT64_ARRAY(env.sp_el, ARMCPU, 4), /* The length-check must come before the arrays to avoid * incoming data possibly overflowing the array. */ -- 1.8.3.2