[Qemu-devel] [PATCH v1 0/5] MicroBlaze queue

[Qemu-devel] [PATCH v1 0/5] MicroBlaze queue

[Edgar E. Iglesias]

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

These are some patches sitting in my queue that I'd like to push out.

Cheers,
Edgar

Edgar E. Iglesias (2):
  microblaze: Support loading of u-boot initrd images
  microblaze: Respect the reset vector

Guenter Roeck (2):
  xilinx_intc: Fix writes into MER register
  xilinx_timer: Fix writes into TCSR register

Peter Crosthwaite (1):
  microblaze: boot: Don't hack the elf entry point

 hw/intc/xilinx_intc.c   |  3 +++
 hw/microblaze/boot.c    | 14 ++++++++++----
 hw/timer/xilinx_timer.c |  2 +-
 target-microblaze/cpu.c |  2 ++
 4 files changed, 16 insertions(+), 5 deletions(-)

-- 
1.8.3.2

[Qemu-devel] [PATCH v1 1/5] microblaze: Support loading of u-boot initrd images

[Edgar E. Iglesias]

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 hw/microblaze/boot.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/hw/microblaze/boot.c b/hw/microblaze/boot.c
index 48d9e7a..deeecfc 100644
--- a/hw/microblaze/boot.c
+++ b/hw/microblaze/boot.c
@@ -174,9 +174,15 @@ void microblaze_load_kernel(MicroBlazeCPU *cpu, hwaddr ddr_base,
             high = ROUND_UP(high + kernel_size, 4);
             boot_info.initrd_start = high;
             initrd_offset = boot_info.initrd_start - ddr_base;
-            initrd_size = load_image_targphys(initrd_filename,
-                                              boot_info.initrd_start,
-                                              ram_size - initrd_offset);
+
+            initrd_size = load_ramdisk(initrd_filename,
+                                       boot_info.initrd_start,
+                                       ram_size - initrd_offset);
+            if (initrd_size < 0) {
+                initrd_size = load_image_targphys(initrd_filename,
+                                                  boot_info.initrd_start,
+                                                  ram_size - initrd_offset);
+            }
             if (initrd_size < 0) {
                 error_report("qemu: could not load initrd '%s'\n",
                              initrd_filename);
-- 
1.8.3.2

[Qemu-devel] [PATCH v1 2/5] microblaze: Respect the reset vector

[Edgar E. Iglesias]

From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 target-microblaze/cpu.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
index 8e04811..0379f2b 100644
--- a/target-microblaze/cpu.c
+++ b/target-microblaze/cpu.c
@@ -96,6 +96,8 @@ static void mb_cpu_reset(CPUState *s)
     env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family.  */
     env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
 
+    env->sregs[SR_PC] = cpu->base_vectors;
+
 #if defined(CONFIG_USER_ONLY)
     /* start in user mode with interrupts enabled.  */
     env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM;
-- 
1.8.3.2

[Qemu-devel] [PATCH v1 3/5] xilinx_intc: Fix writes into MER register

[Edgar E. Iglesias]

From: Guenter Roeck <linux@roeck-us.net>

The MER register only has two valid bits. This is now used by
the linux kernel to auto-detect endianness, and causes Linux 3.15-rc1
and later to hang when run under qemu-microblaze. Mask valid bits before
writing the register to solve the problem.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
[Edgar: Untabified]
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
---
 hw/intc/xilinx_intc.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c
index 1b228ff..c3682f1 100644
--- a/hw/intc/xilinx_intc.c
+++ b/hw/intc/xilinx_intc.c
@@ -121,6 +121,9 @@ pic_write(void *opaque, hwaddr addr,
         case R_CIE:
             p->regs[R_IER] &= ~value; /* Atomic clear ie.  */
             break;
+        case R_MER:
+            p->regs[R_MER] = value & 0x3;
+            break;
         case R_ISR:
             if ((p->regs[R_MER] & 2)) {
                 break;
-- 
1.8.3.2

[Qemu-devel] [PATCH v1 4/5] xilinx_timer: Fix writes into TCSR register

[Edgar E. Iglesias]

From: Guenter Roeck <linux@roeck-us.net>

The TCSR register has only 11 valid bits. This is now used by the
linux kernel to auto-detect endianness, and causes Linux 3.15-rc1
and later to hang when run under qemu-microblaze. Mask valid bits
before writing the register to solve the problem.

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
---
 hw/timer/xilinx_timer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c
index 6113b97..3ff1da9 100644
--- a/hw/timer/xilinx_timer.c
+++ b/hw/timer/xilinx_timer.c
@@ -169,7 +169,7 @@ timer_write(void *opaque, hwaddr addr,
             if (value & TCSR_TINT)
                 value &= ~TCSR_TINT;
 
-            xt->regs[addr] = value;
+            xt->regs[addr] = value & 0x7ff;
             if (value & TCSR_ENT)
                 timer_enable(xt);
             break;
-- 
1.8.3.2

[Qemu-devel] [PATCH v1 5/5] microblaze: boot: Don't hack the elf entry point

[Edgar E. Iglesias]

From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

There was some modulo logic to ensure that Microblaze always booted into
physical RAM regardless of the elf entry. Removed it, as QEMU should fail
gracefully when given a bad elf, rather than attempt to run it.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
 hw/microblaze/boot.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/microblaze/boot.c b/hw/microblaze/boot.c
index deeecfc..6bf36d0 100644
--- a/hw/microblaze/boot.c
+++ b/hw/microblaze/boot.c
@@ -148,7 +148,7 @@ void microblaze_load_kernel(MicroBlazeCPU *cpu, hwaddr ddr_base,
                                    big_endian, ELF_MACHINE, 0);
         }
         /* Always boot into physical ram.  */
-        boot_info.bootstrap_pc = ddr_base + (entry & 0x0fffffff);
+        boot_info.bootstrap_pc = (uint32_t)entry;
 
         /* If it wasn't an ELF image, try an u-boot image.  */
         if (kernel_size < 0) {
-- 
1.8.3.2

Re: [Qemu-devel] [PATCH v1 1/5] microblaze: Support loading of u-boot initrd images

[Peter Crosthwaite]

On Thu, May 8, 2014 at 11:35 AM, Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

> ---
>  hw/microblaze/boot.c | 12 +++++++++---
>  1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/hw/microblaze/boot.c b/hw/microblaze/boot.c
> index 48d9e7a..deeecfc 100644
> --- a/hw/microblaze/boot.c
> +++ b/hw/microblaze/boot.c
> @@ -174,9 +174,15 @@ void microblaze_load_kernel(MicroBlazeCPU *cpu, hwaddr ddr_base,
>              high = ROUND_UP(high + kernel_size, 4);
>              boot_info.initrd_start = high;
>              initrd_offset = boot_info.initrd_start - ddr_base;
> -            initrd_size = load_image_targphys(initrd_filename,
> -                                              boot_info.initrd_start,
> -                                              ram_size - initrd_offset);
> +
> +            initrd_size = load_ramdisk(initrd_filename,
> +                                       boot_info.initrd_start,
> +                                       ram_size - initrd_offset);
> +            if (initrd_size < 0) {
> +                initrd_size = load_image_targphys(initrd_filename,
> +                                                  boot_info.initrd_start,
> +                                                  ram_size - initrd_offset);
> +            }
>              if (initrd_size < 0) {
>                  error_report("qemu: could not load initrd '%s'\n",
>                               initrd_filename);
> --
> 1.8.3.2
>
>

Re: [Qemu-devel] [PATCH v1 2/5] microblaze: Respect the reset vector

[Peter Crosthwaite]

On Thu, May 8, 2014 at 11:35 AM, Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>

Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

> ---
>  target-microblaze/cpu.c | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
> index 8e04811..0379f2b 100644
> --- a/target-microblaze/cpu.c
> +++ b/target-microblaze/cpu.c
> @@ -96,6 +96,8 @@ static void mb_cpu_reset(CPUState *s)
>      env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family.  */
>      env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
>
> +    env->sregs[SR_PC] = cpu->base_vectors;
> +
>  #if defined(CONFIG_USER_ONLY)
>      /* start in user mode with interrupts enabled.  */
>      env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM;
> --
> 1.8.3.2
>
>

Re: [Qemu-devel] [PATCH v1 3/5] xilinx_intc: Fix writes into MER register

[Peter Crosthwaite]

On Thu, May 8, 2014 at 11:35 AM, Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
> From: Guenter Roeck <linux@roeck-us.net>
>
> The MER register only has two valid bits. This is now used by
> the linux kernel to auto-detect endianness, and causes Linux 3.15-rc1
> and later to hang when run under qemu-microblaze. Mask valid bits before
> writing the register to solve the problem.
>
> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
> [Edgar: Untabified]
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>

Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>

> ---
>  hw/intc/xilinx_intc.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c
> index 1b228ff..c3682f1 100644
> --- a/hw/intc/xilinx_intc.c
> +++ b/hw/intc/xilinx_intc.c
> @@ -121,6 +121,9 @@ pic_write(void *opaque, hwaddr addr,
>          case R_CIE:
>              p->regs[R_IER] &= ~value; /* Atomic clear ie.  */
>              break;
> +        case R_MER:
> +            p->regs[R_MER] = value & 0x3;
> +            break;

We probably should macroify the whole core at some point.

Regards,
Peter

>          case R_ISR:
>              if ((p->regs[R_MER] & 2)) {
>                  break;
> --
> 1.8.3.2
>
>

Re: [Qemu-devel] [PATCH v1 4/5] xilinx_timer: Fix writes into TCSR register

[Peter Crosthwaite]

On Thu, May 8, 2014 at 11:35 AM, Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
> From: Guenter Roeck <linux@roeck-us.net>
>
> The TCSR register has only 11 valid bits. This is now used by the
> linux kernel to auto-detect endianness, and causes Linux 3.15-rc1
> and later to hang when run under qemu-microblaze. Mask valid bits
> before writing the register to solve the problem.
>
> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
> ---
>  hw/timer/xilinx_timer.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c
> index 6113b97..3ff1da9 100644
> --- a/hw/timer/xilinx_timer.c
> +++ b/hw/timer/xilinx_timer.c
> @@ -169,7 +169,7 @@ timer_write(void *opaque, hwaddr addr,
>              if (value & TCSR_TINT)
>                  value &= ~TCSR_TINT;
>
> -            xt->regs[addr] = value;
> +            xt->regs[addr] = value & 0x7ff;

In at least the later TRMs, Bit 11 is validly defined as the cascade
bit, taking the total number of bits to 12. I think this mask should
be 0xfff.

Regards,
Peter

>              if (value & TCSR_ENT)
>                  timer_enable(xt);
>              break;
> --
> 1.8.3.2
>
>

Re: [Qemu-devel] [PATCH v1 4/5] xilinx_timer: Fix writes into TCSR register

[Edgar E. Iglesias]

On Thu, May 08, 2014 at 12:45:03PM +1000, Peter Crosthwaite wrote:
> On Thu, May 8, 2014 at 11:35 AM, Edgar E. Iglesias
> <edgar.iglesias@gmail.com> wrote:
> > From: Guenter Roeck <linux@roeck-us.net>
> >
> > The TCSR register has only 11 valid bits. This is now used by the
> > linux kernel to auto-detect endianness, and causes Linux 3.15-rc1
> > and later to hang when run under qemu-microblaze. Mask valid bits
> > before writing the register to solve the problem.
> >
> > Signed-off-by: Guenter Roeck <linux@roeck-us.net>
> > Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
> > Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
> > ---
> >  hw/timer/xilinx_timer.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c
> > index 6113b97..3ff1da9 100644
> > --- a/hw/timer/xilinx_timer.c
> > +++ b/hw/timer/xilinx_timer.c
> > @@ -169,7 +169,7 @@ timer_write(void *opaque, hwaddr addr,
> >              if (value & TCSR_TINT)
> >                  value &= ~TCSR_TINT;
> >
> > -            xt->regs[addr] = value;
> > +            xt->regs[addr] = value & 0x7ff;
> 
> In at least the later TRMs, Bit 11 is validly defined as the cascade
> bit, taking the total number of bits to 12. I think this mask should
> be 0xfff.

Hi,

For timer versions without cascading support, bit 11 is reserved.
I think the patch is good. Once someone adds cascading support we
can expose and implement the cascading bit + the necessary
additional regs.

Cheers,
Edgar