From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52772) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WiRQp-00068X-CC for qemu-devel@nongnu.org; Thu, 08 May 2014 12:44:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WiRQh-0003GE-KQ for qemu-devel@nongnu.org; Thu, 08 May 2014 12:44:27 -0400 Received: from mx1.redhat.com ([209.132.183.28]:51773) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WiRQh-0003G3-DL for qemu-devel@nongnu.org; Thu, 08 May 2014 12:44:19 -0400 From: Paolo Bonzini Date: Thu, 8 May 2014 18:09:45 +0200 Message-Id: <1399565391-27833-6-git-send-email-pbonzini@redhat.com> In-Reply-To: <1399565391-27833-1-git-send-email-pbonzini@redhat.com> References: <1399565391-27833-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [RFC PATCH 05/11] softmmu: move ALIGNED_ONLY to cpu.h List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, rth@twiddle.net Prepare for moving softmmu_header.h inclusion out of .c files Signed-off-by: Paolo Bonzini --- target-alpha/cpu.h | 1 + target-alpha/mem_helper.c | 1 - target-mips/cpu.h | 1 + target-mips/op_helper.c | 1 - target-sparc/cpu.h | 2 ++ target-sparc/ldst_helper.c | 1 - target-xtensa/cpu.h | 1 + target-xtensa/op_helper.c | 1 - 8 files changed, 5 insertions(+), 4 deletions(-) diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h index 07d9f63..d9b861f 100644 --- a/target-alpha/cpu.h +++ b/target-alpha/cpu.h @@ -24,6 +24,7 @@ #include "qemu-common.h" #define TARGET_LONG_BITS 64 +#define ALIGNED_ONLY #define CPUArchState struct CPUAlphaState diff --git a/target-alpha/mem_helper.c b/target-alpha/mem_helper.c index 5964bdc..fa9e8a3 100644 --- a/target-alpha/mem_helper.c +++ b/target-alpha/mem_helper.c @@ -134,7 +134,6 @@ void alpha_cpu_unassigned_access(CPUState *cs, hwaddr addr, #include "exec/softmmu_exec.h" #define MMUSUFFIX _mmu -#define ALIGNED_ONLY #define SHIFT 0 #include "exec/softmmu_template.h" diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 6c2014e..a9b2c7a 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -3,6 +3,7 @@ //#define DEBUG_OP +#define ALIGNED_ONLY #define TARGET_HAS_ICE 1 #define ELF_MACHINE EM_MIPS diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 4edec6c..209dcdf 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -2133,7 +2133,6 @@ static void QEMU_NORETURN do_unaligned_access(CPUMIPSState *env, int is_user, uintptr_t retaddr); #define MMUSUFFIX _mmu -#define ALIGNED_ONLY #define SHIFT 0 #include "exec/softmmu_template.h" diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index f72451d..836f87f 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -5,6 +5,8 @@ #include "qemu-common.h" #include "qemu/bswap.h" +#define ALIGNED_ONLY + #if !defined(TARGET_SPARC64) #define TARGET_LONG_BITS 32 #define TARGET_DPREGS 16 diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c index ec14802..d676f16 100644 --- a/target-sparc/ldst_helper.c +++ b/target-sparc/ldst_helper.c @@ -70,7 +70,6 @@ static void QEMU_NORETURN do_unaligned_access(CPUSPARCState *env, int is_user, uintptr_t retaddr); #include "exec/softmmu_exec.h" #define MMUSUFFIX _mmu -#define ALIGNED_ONLY #define SHIFT 0 #include "exec/softmmu_template.h" diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index e210bac..d797d26 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -28,6 +28,7 @@ #ifndef CPU_XTENSA_H #define CPU_XTENSA_H +#define ALIGNED_ONLY #define TARGET_LONG_BITS 32 #define ELF_MACHINE EM_XTENSA diff --git a/target-xtensa/op_helper.c b/target-xtensa/op_helper.c index b531019..a2439be 100644 --- a/target-xtensa/op_helper.c +++ b/target-xtensa/op_helper.c @@ -34,7 +34,6 @@ static void do_unaligned_access(CPUXtensaState *env, target_ulong addr, int is_write, int is_user, uintptr_t retaddr); -#define ALIGNED_ONLY #define MMUSUFFIX _mmu #define SHIFT 0 -- 1.8.3.1