From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46930) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WkCHb-0003BV-Pz for qemu-devel@nongnu.org; Tue, 13 May 2014 08:58:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WkCHS-000877-P9 for qemu-devel@nongnu.org; Tue, 13 May 2014 08:58:11 -0400 Received: from mail-ee0-x234.google.com ([2a00:1450:4013:c00::234]:39754) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WkCHS-00086w-JK for qemu-devel@nongnu.org; Tue, 13 May 2014 08:58:02 -0400 Received: by mail-ee0-f52.google.com with SMTP id e53so390671eek.39 for ; Tue, 13 May 2014 05:58:01 -0700 (PDT) Sender: Paolo Bonzini From: Paolo Bonzini Date: Tue, 13 May 2014 14:57:24 +0200 Message-Id: <1399985844-788-16-git-send-email-pbonzini@redhat.com> In-Reply-To: <1399985844-788-1-git-send-email-pbonzini@redhat.com> References: <1399985844-788-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PULL 15/15] pc: port 92 reset requires a low->high transition List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paolo Bonzini The PIIX datasheet says that "before another INIT pulse can be generated via [port 92h], [bit 0] must be written back to a zero. This bug is masked right now because a full reset will clear the value of port 92h. But once we implement soft reset correctly, the next attempt to enable the A20 line by setting bit 1 (and leaving the others untouched) will cause another reset. Reviewed-by: Anthony Liguori Reviewed-by: Michael S. Tsirkin Signed-off-by: Paolo Bonzini --- hw/i386/pc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 07de238..e6369d5 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -471,11 +471,12 @@ static void port92_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { Port92State *s = opaque; + int oldval = s->outport; DPRINTF("port92: write 0x%02x\n", val); s->outport = val; qemu_set_irq(*s->a20_out, (val >> 1) & 1); - if (val & 1) { + if ((val & 1) && !(oldval & 1)) { qemu_system_reset_request(); } } -- 1.8.3.1