From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54788) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WkFOs-0007D7-41 for qemu-devel@nongnu.org; Tue, 13 May 2014 12:18:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1WkFOj-0005Xc-N2 for qemu-devel@nongnu.org; Tue, 13 May 2014 12:17:54 -0400 Received: from edge10.ethz.ch ([82.130.75.186]:24924) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1WkFOj-0005Vy-Gz for qemu-devel@nongnu.org; Tue, 13 May 2014 12:17:45 -0400 From: Fabian Aggeler Date: Tue, 13 May 2014 18:15:54 +0200 Message-ID: <1399997768-32014-10-git-send-email-aggelerf@ethz.ch> In-Reply-To: <1399997768-32014-1-git-send-email-aggelerf@ethz.ch> References: <1399997768-32014-1-git-send-email-aggelerf@ethz.ch> MIME-Version: 1.0 Content-Type: text/plain Subject: [Qemu-devel] [PATCH v2 09/23] target-arm: add non-secure Translation Block flag List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: edgar.iglesias@gmail.com, Sergey Fedorov , Fabian Aggeler , peter.maydell@linaro.org From: Sergey Fedorov This patch is based on idea found in patch at git://github.com/jowinter/qemu-trustzone.git f3d955c6c0ed8c46bc0eb10b634201032a651dd2 by Johannes Winter . This flag prevents from executing TCG code generated for other CPU secure state. It also allows to generate different TCG code depending on CPU secure state. Signed-off-by: Sergey Fedorov Signed-off-by: Fabian Aggeler --- target-arm/cpu.h | 7 +++++++ target-arm/translate.c | 3 +++ target-arm/translate.h | 1 + 3 files changed, 11 insertions(+) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index 717b2e7..f86a101 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -1133,6 +1133,8 @@ static inline int cpu_mmu_index (CPUARMState *env) #define ARM_TBFLAG_BSWAP_CODE_MASK (1 << ARM_TBFLAG_BSWAP_CODE_SHIFT) #define ARM_TBFLAG_CPACR_FPEN_SHIFT 17 #define ARM_TBFLAG_CPACR_FPEN_MASK (1 << ARM_TBFLAG_CPACR_FPEN_SHIFT) +#define ARM_TBFLAG_NS_SHIFT 18 +#define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT) /* Bit usage when in AArch64 state */ #define ARM_TBFLAG_AA64_EL_SHIFT 0 @@ -1163,6 +1165,8 @@ static inline int cpu_mmu_index (CPUARMState *env) (((F) & ARM_TBFLAG_AA64_EL_MASK) >> ARM_TBFLAG_AA64_EL_SHIFT) #define ARM_TBFLAG_AA64_FPEN(F) \ (((F) & ARM_TBFLAG_AA64_FPEN_MASK) >> ARM_TBFLAG_AA64_FPEN_SHIFT) +#define ARM_TBFLAG_NS(F) \ + (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT) static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, int *flags) @@ -1192,6 +1196,9 @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, if (privmode) { *flags |= ARM_TBFLAG_PRIV_MASK; } + if (!arm_is_secure(env)) { + *flags |= ARM_TBFLAG_NS_MASK; + } if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) || arm_el_is_aa64(env, 1)) { *flags |= ARM_TBFLAG_VFPEN_MASK; diff --git a/target-arm/translate.c b/target-arm/translate.c index 46553fa..87d0918 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -53,8 +53,10 @@ static uint32_t gen_opc_condexec_bits[OPC_BUF_SIZE]; #if defined(CONFIG_USER_ONLY) #define IS_USER(s) 1 +#define IS_NS(s) 1 #else #define IS_USER(s) (s->user) +#define IS_NS(s) (s->ns) #endif TCGv_ptr cpu_env; @@ -10783,6 +10785,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, dc->condexec_cond = ARM_TBFLAG_CONDEXEC(tb->flags) >> 4; #if !defined(CONFIG_USER_ONLY) dc->user = (ARM_TBFLAG_PRIV(tb->flags) == 0); + dc->ns = ARM_TBFLAG_NS(tb->flags); #endif dc->cpacr_fpen = ARM_TBFLAG_CPACR_FPEN(tb->flags); dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags); diff --git a/target-arm/translate.h b/target-arm/translate.h index 34328f4..5732738 100644 --- a/target-arm/translate.h +++ b/target-arm/translate.h @@ -19,6 +19,7 @@ typedef struct DisasContext { int bswap_code; #if !defined(CONFIG_USER_ONLY) int user; + int ns; #endif bool cpacr_fpen; /* FP enabled via CPACR.FPEN */ bool vfp_enabled; /* FP enabled via FPSCR.EN */ -- 1.8.3.2